VSQRTSH

VSQRTSH takes the square root of the low half of its second source and rounds it correctly, under MXCSR.RC or, between registers, under a rounding mode given in the instruction ({er}). Bits 127:16 come from the first source and the bits above 127 are cleared, as VSQRTSS does for singles; that page shows why compilers name a register the root already depends on as that first source. It is the scalar form of VSQRTPH, opcode 51h with the F3 prefix in EVEX map 5, takes a write mask on the low half, and reads two bytes when its source is in memory. Like the packed form it reports only invalid, precision and denormal, and the special inputs are those of SQRTPS: -0 gives -0 and any other negative input is invalid. VADDPH covers the format, the CPUID bits and FP16’s use of MXCSR.

sqrtf16 and errno#

C’s square root functions may set errno for a negative argument, which no instruction does. At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 compiles __builtin_sqrtf16(x) to vsqrtsh xmm1, xmm0, xmm0, then compares the result with itself by VUCOMISH and calls the library’s sqrtf16 only when it is a NaN; Clang 23 calls sqrtf16 every time. With -fno-math-errno both give the one instruction vsqrtsh xmm0, xmm0, xmm0. _mm_sqrt_sh(a, b) becomes vsqrtsh xmm0, xmm0, xmm1, the low half of b with the rest of a.

A root taken in single precision#

(_Float16)sqrtf((float)x) widens the half, takes a single-precision root and narrows it again. GCC replaces all of that with VSQRTSH: with -fno-math-errno the function is that one instruction, and without it GCC keeps only a test of the widened argument against zero, made with VCVTSH2SS and VUCOMISS, for the call that sets errno. Clang keeps the three steps, VCVTSH2SS, VSQRTSS and VCVTSS2SH.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VSQRTSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f16[0] = sqrt(src3.f16[0])
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSQRTSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions