VSQRTSS

VSQRTSS is SQRTSS in VEX and EVEX encodings: the root of the low single of its last operand, with singles 1 to 3 copied from the operand before it and the bits above 127 cleared. The SQRTSS page covers the special inputs and the test that C’s errno needs, and VSQRTPS the packed forms. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1.

A source for the upper singles#

SQRTSS merges its root into the old destination and so waits for whatever last wrote that register. Here the upper singles come from a named source, and compilers name a register the root already depends on. In our builds with -march=x86-64-v3 or x86-64-v4 and -fno-math-errno, GCC 14 and Clang 23 compile sqrtf(x) to vsqrtss xmm0, xmm0, xmm0, and for sqrtf(x * x + y * y) Clang writes vsqrtss xmm0, xmm1, xmm1, whose only input is the sum in XMM1. _mm_sqrt_ss(a) becomes the same three-register form.

Zen 5’s VEX cases show the split. With MXCSR at 7F80H (round toward zero), the root of the smallest denormal, 2^-149, read from memory, was the normal 1A3504F3H, about 3.7e-23, with DE and PE set; singles 1 to 3 came from the first source, and bits 511:128 of the destination were cleared.

The EVEX forms#

Masking applies to the low single only, and the upper singles are copied either way. vsqrtss xmm7{k6}, xmm12, xmm7, {ru-sae} ran with bit 0 of K6 clear: no root was taken, the low single kept the destination’s old value, the largest single, and singles 1 to 3 still came from XMM12. With {z} the low single would be zeroed instead.

Unlike the packed forms, which take a rounding mode in the instruction only between 512-bit registers, the scalar EVEX form takes one on xmm registers: _mm_mask_sqrt_round_ss with _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC gives vsqrtss xmm0{k1}, xmm1, xmm2, {ru-sae} in both compilers. EVEX also reaches XMM16 to XMM31, as in the recorded vsqrtss xmm17{k7}{z}, xmm30, dword ptr [mem].

AMD’s latency spreadsheet for Zen 5 lists it at 14 cycles and 0.222 per cycle on pipe FP1, like SQRTSS. VSQRTSD is the double form.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    xmm1.f32[0] = sqrt(src3.f32[0])
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSQRTSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions