Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

VSUBBF16 subtracts the bfloat16 values of its second source from those of its first, element by element, 8, 16 or 32 per register. It is the AVX10.2 counterpart of VSUBPH, with the fixed rules that VADDBF16’s page sets out: rounding to nearest even, denormal inputs and results taken as zeros, no exceptions and no MXCSR. Its opcode is 5Ch in EVEX map 5 with the 66 prefix and W0, where VSUBPH has no prefix; it takes a write mask and a broadcast from 16 bits of memory, and has no scalar form.

Differences that vanish

Flushing results to zero breaks a rule that IEEE arithmetic keeps: with gradual underflow, x - y is zero only when x equals y. Here 00C0h minus 0080h, 1.5 × 2^-126 minus 2^-126, is 2^-127, a denormal, and VSUBBF16 returns zero. Code that guards a division with x != y can still divide by zero, which the instruction does not report either.

In our builds

GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 vectorizes Z[i] = X[i] - Y[i] over global __bf16 arrays into VSUBBF16 on zmm registers with the second source from memory, but X[i] - 3 becomes VADDBF16 with -3 broadcast from a constant. A single __bf16 difference is widened to singles, subtracted with VSUBSS and narrowed with VCVTNEPS2BF16, which also reads a denormal single as zero, so that path gives zero for the example above too. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Every encoding of VSUBBF16 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VSUBBF16 xmm {k}{z}, xmm, xmm VSUBBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512EVEX.128.66.MAP5.W0 5C /rAVX10.2
VSUBBF16 xmm {k}{z}, xmm, m128/m16bcst VSUBBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512EVEX.128.66.MAP5.W0 5C /rAVX10.2
VSUBBF16 ymm {k}{z}, ymm, ymm VSUBBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512EVEX.256.66.MAP5.W0 5C /rAVX10.2
VSUBBF16 ymm {k}{z}, ymm, m256/m16bcst VSUBBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512EVEX.256.66.MAP5.W0 5C /rAVX10.2
VSUBBF16 zmm {k}{z}, zmm, zmm VSUBBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512EVEX.512.66.MAP5.W0 5C /rAVX10.2
VSUBBF16 zmm {k}{z}, zmm, m512/m16bcst VSUBBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512EVEX.512.66.MAP5.W0 5C /rAVX10.2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each bfloat16 of the result comes from the bfloat16 in the same place in each source.
VSUBBF16: element by elementResult bfloat16 i comes from bfloat16 i of xmm2 and xmm3. Result bfloat16s 7 to 0: a7-b7, unchanged (bit 6 of k1 is 0), a5-b5, a4-b4, a3-b3, a2-b2, a1-b1, a0-b0.01234567xmm2a11111110k1a0-b0a1-b1a2-b2a3-b3a4-b4a5-b5a7-b7xmm101234567xmm3or m128b

Every bfloat16 works alike: 8, 16 and 32 bfloat16s in the xmm, ymm and zmm forms. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m16bcst, one bfloat16 from memory stands for every element of the last source.

Result bfloat16 i comes from bfloat16 i of xmm2 and xmm3. Result bfloat16s 7 to 0: a7-b7, unchanged (bit 6 of k1 is 0), a5-b5, a4-b4, a3-b3, a2-b2, a1-b1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.bf16[i]
        b = src3.bf16[i]
        zmm1.bf16[i] = sub(a, b)
    elif zeroing:
        zmm1.bf16[i] = 0
    # else: zmm1.bf16[i] keeps its value
# m16bcst: src3.bf16[i] is the m16 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Not run on a processor: none of these processors has AVX10.2. The tests check its arithmetic against MPFR.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VSUBBF16 xmm {k}{z}, xmm, xmm/m128/m16bcst VSUBBF16 ymm {k}{z}, ymm, ymm/m256/m16bcst VSUBBF16 zmm {k}{z}, zmm, zmm/m512/m16bcst
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m16bcst, ymm/m256/m16bcst, zmm/m512/m16bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms
write masking; always rounds to nearest even; denormal inputs read as zero; denormal results flushed to zero
Memory forms
embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSUBBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_sub_pbh __m128bh _mm_sub_pbh(__m128bh __A, __m128bh __B)

VSUBBF16 xmm, xmm, xmm EVEX.128 -mavx10.2

_mm_mask_sub_pbh __m128bh _mm_mask_sub_pbh(__m128bh __W, __mmask8 __U, __m128bh __A, __m128bh __B)

VSUBBF16 xmm {k}, xmm, xmm EVEX.128 -mavx10.2

_mm_maskz_sub_pbh __m128bh _mm_maskz_sub_pbh(__mmask8 __U, __m128bh __A, __m128bh __B)

VSUBBF16 xmm {k}{z}, xmm, xmm EVEX.128 -mavx10.2

_mm256_sub_pbh __m256bh _mm256_sub_pbh(__m256bh __A, __m256bh __B)

VSUBBF16 ymm, ymm, ymm EVEX.256 -mavx10.2

_mm256_mask_sub_pbh __m256bh _mm256_mask_sub_pbh(__m256bh __W, __mmask16 __U, __m256bh __A, __m256bh __B)

VSUBBF16 ymm {k}, ymm, ymm EVEX.256 -mavx10.2

_mm256_maskz_sub_pbh __m256bh _mm256_maskz_sub_pbh(__mmask16 __U, __m256bh __A, __m256bh __B)

VSUBBF16 ymm {k}{z}, ymm, ymm EVEX.256 -mavx10.2

_mm512_sub_pbh __m512bh _mm512_sub_pbh(__m512bh __A, __m512bh __B)

VSUBBF16 zmm, zmm, zmm EVEX.512 -mavx10.2

_mm512_mask_sub_pbh __m512bh _mm512_mask_sub_pbh(__m512bh __W, __mmask32 __U, __m512bh __A, __m512bh __B)

VSUBBF16 zmm {k}, zmm, zmm EVEX.512 -mavx10.2

_mm512_maskz_sub_pbh __m512bh _mm512_maskz_sub_pbh(__mmask32 __U, __m512bh __A, __m512bh __B)

VSUBBF16 zmm {k}{z}, zmm, zmm EVEX.512 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX10_2_BF16_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX10_2_BF16_256
Same as AVX10_2_BF16_128Same as AVX10_2_BF16_128
AVX10_2_BF16_512
Same as AVX10_2_BF16_128Same as AVX10_2_BF16_128

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.