VSUBPD

VSUBPD subtracts the doubles of its last operand from those of the one before, two to an xmm register, four to a ymm one and eight to a zmm one. It is SUBPD in VEX and EVEX encodings: VSUBPS covers the order of the operands, the sign of a zero difference and what compilers make of a minus sign, and VADDPD what the encodings add for doubles, down to a broadcast of one 64-bit element. AMD’s Zen 5 guide lists it as it lists VSUBPS: one macro-op on the pipes FP2 and FP3, with a latency of 2 cycles.

Edges recorded on Zen 5#

• With MXCSR rounding down, vsubpd xmm12, xmm6, xmm6 turned 2 - 2 and 0.5 - 0.5 into -0.
• Rounding toward zero, 0.1 broadcast from memory and subtracted from 10^300 gave the double just below 10^300, and subtracted from 10^-300 gave -0.09999999999999999 instead of -0.1. With DAZ set, a denormal minus 0.1 was exactly -0.1.
• The largest denormal minus the smallest normal is -2^-1074, exact and itself a denormal: it came back as such, with DE set for the denormal input but not UE, since nothing was rounded.
• With the denormal exception unmasked, {rn-sae} let a denormal minus itself give +0 without a #XM.
• An element that the write mask leaves out raises nothing: with k1 selecting none of the four, vsubpd ymm24{k1}, ymm3, ymmword ptr [mem] met a signaling NaN, left IE clear and kept the destination’s old elements.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 make b[i] - c[i] over doubles one VSUBPD per four elements, and 1.0 - b[i] one with the broadcast 1 as the first source. Two other shapes avoid it:

• b[i] * c[i] - d[i] becomes a fused multiply-subtract, VFMSUB132PD in GCC and VFMSUB213PD in Clang, rounded once. GCC keeps VMULPD and VSUBPD under -std=c17, which turns contraction off; Clang contracts either way.
• A loop that subtracts in its even elements and adds in its odd ones becomes VADDSUBPD in both.

In the optimization guide

What the optimization guide says about VSUBPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Zeroing and dependency-breaking idioms: A floating-point subtraction of a register from itself is not a safe way to zero it, since a NaN input gives NaN. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f64[i]
        b = src3.f64[i]
        zmm1.f64[i] = sub(a, b)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSUBPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions