VSUBPH

VSUBPH subtracts the halves of its last operand from those of the one before, 32 per zmm register: vsubph zmm0, zmm1, zmm2 computes zmm1 - zmm2. It is VADDPH with the second operand’s sign flipped, and that page covers the format, the CPUID bits and the encoding; VSUBPH has opcode 5Ch in EVEX map 5, that of SUBPS. It rounds by MXCSR.RC, or by {er} on the 512-bit register form, and reports the same five exceptions as VSUBPS, whose page gives the sign of a zero difference: +0, except -0 when rounding toward negative infinity.

No flushing to zero#

Intel’s optimization manual says FP16 arithmetic ignores MXCSR.FTZ and DAZ (Section 18.5.4), so a difference too small for a normal half becomes a denormal, never a zero. Two different halves therefore never subtract to 0, which singles under FTZ can: near the bottom of the half range, at 2^-14, a step of one unit in the last place is only 2^-24, so differences that small arise easily.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile c[i] = a[i] - b[i] over global _Float16 arrays to VSUBPH with b[i] from memory, GCC on zmm and Clang on ymm registers. Through pointers and with an unknown length, GCC keeps one VSUBSH per element at -O2 and vectorizes at -O3; Clang vectorizes behind a check that the arrays do not overlap. For 1 - a[i] the 1 is held in a register as first source, subtracting a constant 1 becomes VADDPH of -1, and -a[i] flips the sign bits with an exclusive or against 8000h (VPXORD in GCC, VPXOR in Clang), as for singles. Without AVX512-FP16, as with -march=znver5, both widen with VCVTPH2PS, subtract singles and narrow with VCVTPS2PH, GCC one element at a time and Clang sixteen.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VSUBPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.f16[i]
        b = src3.f16[i]
        zmm1.f16[i] = sub(a, b)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSUBPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions