VSUBPS

VSUBPS subtracts the singles of its last operand from those of the one before: vsubps ymm0, ymm1, ymm2 computes ymm1 - ymm2. It is SUBPS in VEX and EVEX encodings, with what VADDPS shows for them (a separate destination, the bits above the result cleared, masking, a broadcast single, a rounding mode in the instruction) and the rounding of ADDPS: the difference is the sum with the second operand’s sign flipped, so an infinity minus an infinity of the same sign is the invalid case. On Zen 5 it gave the indefinite FFC00000H and set IE.

The sign of a zero difference#

A zero difference of two operands of like sign is +0 in every rounding mode but one: rounding toward negative infinity gives -0. Intel’s manual states the rule with the x87 FSUB, and Volume 1 lists the same results for the fused multiply-adds (Table 14-16). Zen 5’s recorded cases show both signs: with MXCSR rounding down, the largest single minus itself was -0; rounding up, 10^30 minus itself was +0.

What compilers make of a minus sign#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 keep VSUBPS only where nothing else gives the same result:

• b[i] - c[i] and 1.0f - b[i] are VSUBPS. There is no reversed form, so the 1 sits in a register as the first source and b[i] comes from memory as the second.
• b[i] - 1.0f becomes VADDPS of -1, which is the same operation.
• -b[i] is not 0 - b[i]: it is a VXORPS with -0.0 that flips the sign bits, since -(+0) is -0 and 0 - (+0) is +0. 0.0f - b[i] stays a VSUBPS from a zeroed register.
• b[i] - b[i] stays a VSUBPS of a register from itself rather than a constant 0, as an infinity or a NaN gives a NaN.

On Zen 5#

AMD’s Zen 5 guide lists VSUBPS as it lists VADDPS: one macro-op on the pipes FP2 and FP3, with a latency of 2 cycles at every width.

In the optimization guide

What the optimization guide says about VSUBPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Zeroing and dependency-breaking idioms: A floating-point subtraction of a register from itself is not a safe way to zero it, since a NaN input gives NaN. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f32[i]
        b = src3.f32[i]
        zmm1.f32[i] = sub(a, b)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSUBPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions