VSUBSD

VSUBSD is SUBSD in VEX and EVEX encodings: the low double of its last operand subtracted from that of the operand before it, with the high double copied from that first source and the bits above 127 cleared. VSUBSS shows how the separate destination saves the copy that 1.0 - x needs with SUBSD, and VADDSS what else the encodings change. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1.

The fractional part#

The SUBSD page computes x - (long)x through a conversion to an integer and back. With SSE4.1’s rounding available, x - floor(x) is shorter: in our builds with -march=x86-64-v3, GCC 14 and Clang 23 at -O2 emit vroundsd xmm1, xmm0, xmm0, 9 and vsubsd xmm0, xmm0, xmm1. For x86-64-v4, GCC takes VRNDSCALESD for the rounding instead, as VROUNDSD explains; VSUBSD stays.

On Zen 5#

• vsubsd xmm12, xmm6, xmm6, under MXCSR 3FC0H, subtracted the signaling NaN FFF0000000000001H from itself and set IE. The result was that NaN quieted, FFF8000000000001H, which Intel’s Volume 1 gives for two signaling NaNs (Table 4-8).
• The EVEX vsubsd xmm0{k7}, xmm31, xmm16, {rz-sae}, with bit 0 of K7 set, computed the most negative double minus 2: rounded toward zero, the most negative double again. MXCSR (6600H) left the precision exception unmasked, yet {sae} gave no #XM and no PE.
• vsubsd xmm9{k2}{z}, xmm9, qword ptr [mem], with bit 0 of K2 set, computed 3 minus 0.1 under FFC0H (toward zero) as 2.9 (4007333333333333H) and set PE.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows 2 cycles on pipes FP2 and FP3, the figures of SUBSD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm2.f64[0]
    b = src3.f64[0]
    xmm1.f64[0] = sub(a, b)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSUBSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions