VSUBSH

VSUBSH subtracts the low half of its last operand from the low half of the one before, vsubsh xmm0, xmm1, xmm2 giving xmm1 - xmm2 in bits 15:0, and copies bits 127:16 from the first source; the bits above 127 are cleared. It is the scalar form of VSUBPH, whose page says why a difference of two different halves is never zero, and the subtracting twin of VADDSH, which covers what the scalar FP16 forms share: EVEX only, opcode 5Ch with the F3 prefix in map 5, a write mask on the one element, {er} and a 2-byte memory operand. VADDPH has the format and the CPUID bits, and VSUBSS’s page gives the sign of a zero difference, which is the same for halves: +0, except -0 when rounding toward negative infinity.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile x - y on _Float16 values to one VSUBSH and _mm_sub_sh likewise. A running difference s -= a[i] over a _Float16 array is a chain of VSUBSH with each half read from memory; with -ffast-math, GCC subtracts 32 halves at a time with VSUBPH and Clang mixes VSUBPH and VADDPH, both adding up the partial results at the end. At -O2 without that option, GCC computes the fractional part a[i] - truncf16(a[i]) one element at a time, with VRNDSCALESH and VSUBSH, where Clang vectorizes it with VRNDSCALEPH and VSUBPH; neither uses VREDUCEPH, which gives the same result for finite values in one instruction.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VSUBSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f16[0]
    b = src3.f16[0]
    xmm1.f16[0] = sub(a, b)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSUBSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions