VSUBSS

VSUBSS is SUBSS in VEX and EVEX encodings: the low single of its last operand subtracted from that of the operand before it, with singles 1 to 3 copied from that first source and the bits above 127 cleared. VADDSS covers what the encodings change, VSUBPS the sign of a zero difference, and the SUBSS page what C’s subtraction compiles to and which of two NaNs survives. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1.

A constant as the minuend#

SUBSS writes the difference over the minuend, so 1.0f - x needs the 1 in the destination and costs a MOVAPS beside the load, as the SUBSS page shows. With -march=x86-64-v3 or x86-64-v4, GCC 14 and Clang 23 at -O2 load the constant with VMOVSS and write vsubss xmm0, xmm1, xmm0: two instructions, the result already in the register that returns it. For x86-64-v3 the fractional part x - floorf(x) is VROUNDSS into XMM1 and vsubss xmm0, xmm0, xmm1, again without a copy.

On Zen 5#

• vsubss xmm8, xmm15, xmm0, under MXCSR 3FC0H, subtracted -infinity from +infinity and gave +infinity with no flag: only infinities of the same sign make the invalid difference.
• With MXCSR at 7F80H (round toward zero), 3 minus 0.1 from memory gave 2.8999999 (40399999H) and set PE.
• vsubss xmm14{k1}{z}, xmm8, dword ptr [mem], with bit 0 of K1 clear, zeroed the low single and copied the other three, -infinity among them, from XMM8.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows 2 cycles on pipes FP2 and FP3, like VADDSS. VSUBSD is the double form.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm2.f32[0]
    b = src3.f32[0]
    xmm1.f32[0] = sub(a, b)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSUBSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions