VTESTPS instruction (AVX)

In the optimization guide

What the optimization guide says about VTESTPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

Vectors and AVX2: The 256-bit vector tests take 7 cycles from the vectors to the flags.

Forms

Every encoding of VTESTPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VTESTPS xmm, m128` VTESTPS_XMMdq_MEMdq	`VEX.128.66.0F38.W0 0E /r`	AVX
`VTESTPS xmm, xmm` VTESTPS_XMMdq_XMMdq	`VEX.128.66.0F38.W0 0E /r`	AVX
`VTESTPS ymm, m256` VTESTPS_YMMqq_MEMqq	`VEX.256.66.0F38.W0 0E /r`	AVX
`VTESTPS ymm, ymm` VTESTPS_YMMqq_YMMqq	`VEX.256.66.0F38.W0 0E /r`	AVX

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A test of all the sign bits of the singles: ZF is set if xmm1 AND xmm2 is zero, CF if NOT xmm1 AND xmm2 is.

The ymm forms test all 256 bits.

ZF and CF each depend on every element of xmm1 and xmm2. RFLAGS: CF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

zf = cf = 1
for i in range(VL // 32):
    if (ymm1.d[i] & src2.d[i]) >> 31:
        zf = 0
    if (~ymm1.d[i] & src2.d[i]) >> 31:
        cf = 0
of = sf = af = pf = 0

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VTESTPS xmm, xmm/m128` `VTESTPS ymm, ymm/m256`
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified; blank: not affected. How to read.

ZF	CF
All forms
M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VTESTPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_testc_ps` `int _mm_testc_ps(__m128 __a, __m128 __b)`	`VTESTPS xmm, xmm` VEX.128 -mavx
`_mm_testnzc_ps` `int _mm_testnzc_ps(__m128 __a, __m128 __b)`	`VTESTPS xmm, xmm` VEX.128 -mavx
`_mm_testz_ps` `int _mm_testz_ps(__m128 __a, __m128 __b)`	`VTESTPS xmm, xmm` VEX.128 -mavx
`_mm256_testc_ps` `int _mm256_testc_ps(__m256 __a, __m256 __b)`	`VTESTPS ymm, ymm` VEX.256 -mavx
`_mm256_testnzc_ps` `int _mm256_testnzc_ps(__m256 __a, __m256 __b)`	`VTESTPS ymm, ymm` VEX.256 -mavx
`_mm256_testz_ps` `int _mm256_testz_ps(__m256 __a, __m256 __b)`	`VTESTPS ymm, ymm` VEX.256 -mavx

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions