Instruction
VUCOMISD
Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception.
- Extensions
- Forms
- 4 (2 VEX, 2 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VUCOMISD xmm, m64
VUCOMISD_XMMdq_MEMq | VEX.LIG.66.0F.WIG 2E /r | AVX |
VUCOMISD xmm, xmm
VUCOMISD_XMMdq_XMMq | VEX.LIG.66.0F.WIG 2E /r | AVX |
VUCOMISD xmm, xmm, {sae}
VUCOMISD_XMMf64_XMMf64_AVX512 | EVEX.LIG.66.0F.W1 2E /r | AVX10.1 or AVX512F |
VUCOMISD xmm, m64
VUCOMISD_XMMf64_MEMf64_AVX512 | EVEX.LIG.66.0F.W1 2E /r | AVX10.1 or AVX512F |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VUCOMISD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_ucomieq_sd
int _mm_ucomieq_sd(__m128d __a, __m128d __b) |
|
_mm_ucomige_sd
int _mm_ucomige_sd(__m128d __a, __m128d __b) |
|
_mm_ucomigt_sd
int _mm_ucomigt_sd(__m128d __a, __m128d __b) |
|
_mm_ucomile_sd
int _mm_ucomile_sd(__m128d __a, __m128d __b) |
|
_mm_ucomilt_sd
int _mm_ucomilt_sd(__m128d __a, __m128d __b) |
|
_mm_ucomineq_sd
int _mm_ucomineq_sd(__m128d __a, __m128d __b) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX | AVX | Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2 |
AVX512F_SCALAR | AVX10.1 or AVX512F | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill |
More AVX10.1 instructions
- VRSQRT14SD
- VRSQRT14SS
- VRSQRTPH
- VRSQRTSH
- VSCALEFPD
- VSCALEFPH
- VSCALEFPS
- VSCALEFSD
- VSCALEFSH
- VSCALEFSS
- VSCATTERDPD
- VSCATTERDPS
- VSCATTERQPD
- VSCATTERQPS
- VSHUFF32X4
- VSHUFF64X2
- VSHUFI32X4
- VSHUFI64X2
- VSHUFPD
- VSHUFPS
- VSQRTPD
- VSQRTPH
- VSQRTPS
- VSQRTSD
- VSQRTSH
- VSQRTSS
- VSUBPD
- VSUBPH
- VSUBPS
- VSUBSD
- VSUBSH
- VSUBSS
- VUCOMISH
- VUCOMISS
- VUNPCKHPD
- VUNPCKHPS
- VUNPCKLPD
- VUNPCKLPS
- VXORPD
- VXORPS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.