VUCOMISD instruction (AVX, AVX10.1)

VUCOMISD is the VEX and EVEX form of UCOMISD, the quiet compare of two low doubles into ZF, PF and CF, which signals invalid only for a signaling NaN. UCOMISD’s page covers how compilers use it, and VCOMISS what the newer encodings add to a compare that writes no register: XMM16 to XMM31 and {sae} in the EVEX form (AVX512F or AVX10.1), and no write mask. The VEX form needs AVX.

Recorded on Zen 5

vucomisd xmm1, qword ptr [mem], a signaling NaN against 1.0 under 7F80H, gave unordered and set IE, MXCSR becoming 7F81H; the EVEX form did the same under FFC0H.
vucomisd xmm1, xmm2 with two quiet NaNs under 3FC0H gave unordered and left MXCSR as it was.
{evex} vucomisd xmm1, xmm2, {sae}, a quiet NaN against 1.0 under 1E40H, where IM is clear and an invalid operation would fault, gave unordered with neither a fault nor a flag: a quiet NaN raises nothing here, {sae} or not.

In compiled code

In our builds at -O2 with -march=x86-64-v3 or -v4, the uses UCOMISD’s page lists take the VEX form: isnan(x) is vucomisd xmm0, xmm0 and SETP in GCC 14 and Clang 23, and GCC tests a == b on doubles with VUCOMISD, SETNP and a CMOVNE that clears the result when ZF is clear. Clang compiles the same == to VCMPEQSD, into an XMM register at -v3 and into K0, read with KMOVW, at -v4. For _mm_comi_round_sd(a, b, _CMP_LE_OQ, _MM_FROUND_CUR_DIRECTION), GCC emits vucomisd xmm1, xmm0 and SETAE, the quiet predicate choosing the quiet compare, and Clang vcmple_oqsd k0, xmm0, xmm1 with KMOVW.

AMD’s latency spreadsheet for Zen 5 lists the VEX and EVEX rows as two macro-ops, on pipes FP2/FP3 and FP4/FP5, two per cycle. VUCOMISS compares singles.

Forms

Every encoding of VUCOMISD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VUCOMISD xmm, m64` VUCOMISD_XMMdq_MEMq	`VEX.LIG.66.0F.WIG 2E /r`	AVX
`VUCOMISD xmm, xmm` VUCOMISD_XMMdq_XMMq	`VEX.LIG.66.0F.WIG 2E /r`	AVX
`VUCOMISD xmm, xmm, {sae}` VUCOMISD_XMMf64_XMMf64_AVX512	`EVEX.LIG.66.0F.W1 2E /r`	AVX10.1 or AVX512F
`VUCOMISD xmm, m64` VUCOMISD_XMMf64_MEMf64_AVX512	`EVEX.LIG.66.0F.W1 2E /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, m64`	`xmm, xmm` `xmm, xmm, {sae}`
Sandy Bridge	8 / 1p01	2 / 1p01
Haswell, Broadwell	8 / 1p1	3 / 1p1
Skylake, Skylake-SP, Ice Lake	7 / 1p0	2 / 1p0
Alder Lake, Sapphire Rapids	8 / 1p0	3 / 1p0
Lunar Lake	9 / 2V0 V1	3 / 1.5V0 V1
Piledriver	6 / 1.5EX0 FPFMA FPU0	1 / 1EX0 FPFMA FPU0
Zen, Zen 2	10 / 1FPU0 FPU1 FPU2	3 / 1FPU0 FPU1 FPU2
Zen 3, Zen 4	11 / 1FP0 FP1	4 / 1FP0 FP1
Jaguar	8 / 1ALU0 FPA FPU0	3 / 1ALU0 FPA FPU0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low doubles of the two sources are compared, and the result sets ZF, PF and CF.

The flags come from double 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = ucomi(xmm1.f64[0], src2.f64[0])  # 0 >, 1 <, 2 =, 3 unordered
zf = x in (2, 3)
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0
# only an SNaN raises IE
# {sae}: no exception flags

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VUCOMISD xmm, xmm/m64` `VUCOMISD xmm, xmm/m64, {sae}`
`xmm`	explicit	read
`xmm/m64`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
VEX forms
0	0	M	0	M	M
EVEX forms
0	0	M	0	M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-3
EVEX forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VUCOMISD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_ucomieq_sd` `int _mm_ucomieq_sd(__m128d __a, __m128d __b)`	`VUCOMISD xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_ucomige_sd` `int _mm_ucomige_sd(__m128d __a, __m128d __b)`	`VUCOMISD xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_ucomigt_sd` `int _mm_ucomigt_sd(__m128d __a, __m128d __b)`	`VUCOMISD xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_ucomile_sd` `int _mm_ucomile_sd(__m128d __a, __m128d __b)`	`VUCOMISD xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_ucomilt_sd` `int _mm_ucomilt_sd(__m128d __a, __m128d __b)`	`VUCOMISD xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_ucomineq_sd` `int _mm_ucomineq_sd(__m128d __a, __m128d __b)`	`VUCOMISD xmm, xmm` VEX.LIG -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512F_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Recorded on Zen 5#

In compiled code#