VUCOMISH instruction (AVX10.1)

VUCOMISH is the quiet twin of VCOMISH: it compares the low halves of two operands into ZF, PF and CF in the same way, and clears OF, SF and AF, but raises the invalid-operation exception only for a signaling NaN, not for a quiet one. That makes it the compare for ==, != and the C99 macros such as isless, which must not signal on a quiet NaN; VUCOMISS and UCOMISS cover the same split for singles. Its opcode is 2Eh in EVEX map 5, it takes {sae} and no write mask, and EVEX.vvvv must be 1111b. VADDPH covers the format; FP16 instructions ignore MXCSR.DAZ, so a denormal half is compared as the value it holds.

In our builds

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 compiles a == b on _Float16 values to VUCOMISH, SETNP and a CMOVNE that clears the result when ZF is clear, and isless(a, b) and isunordered(a, b) to VUCOMISH with SETA and SETP. Clang 23 uses VUCOMISH for <, <= and those macros, and for a branch on == (JNE and JP to skip the call), but for the value of a == b it emits VCMPSH into K0 and KMOVW. _mm_ucomilt_sh became VCMPSH with the quiet predicate _CMP_LT_OQ in both compilers, not VUCOMISH.

Without AVX512-FP16, as with -march=znver5, the compilers widen both halves with VCVTPH2PS and compare the singles with VUCOMISS or VCMPSS. The order comes out the same, since every half is exactly a single, and a signaling NaN still sets IE, in the conversion, as VCVTPH2PS’s page shows; a denormal half, which VUCOMISH may report with DE, becomes a normal single and sets nothing.

AVX10.2 adds VUCOMXSH, opcode 2Eh with an F3 prefix, which also sets OF and SF for the signed conditions. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VUCOMISH.

Forms

Every encoding of VUCOMISH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VUCOMISH xmm, xmm, {sae}` VUCOMISH_XMMf16_XMMf16_AVX512	`EVEX.LIG.NP.MAP5.W0 2E /r`	AVX10.1 or AVX512_FP16
`VUCOMISH xmm, m16` VUCOMISH_XMMf16_MEMf16_AVX512	`EVEX.LIG.NP.MAP5.W0 2E /r`	AVX10.1 or AVX512_FP16

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, xmm, {sae}`	`xmm, m16`
Sapphire Rapids	4 / 1p0	10 / 1p0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low halves of the two sources are compared, and the result sets ZF, PF and CF.

The flags come from half 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = ucomi(xmm1.f16[0], src2.f16[0])  # 0 >, 1 <, 2 =, 3 unordered
zf = x in (2, 3)
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0
# only an SNaN raises IE
# {sae}: no exception flags

Not run on a processor: none of these processors has AVX512-FP16.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VUCOMISH xmm, xmm/m16, {sae}`
`xmm`	explicit	read
`xmm/m16`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512_FP16_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

AVX512_FP16_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

In our builds#