x86-64.net

Instruction

VUCOMISH

Compares the low half-precision values and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception.

Extensions
Forms
2 (2 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VUCOMISH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VUCOMISH xmm, xmm, {sae} VUCOMISH_XMMf16_XMMf16_AVX512EVEX.LIG.NP.MAP5.W0 2E /rAVX10.1 or AVX512_FP16
VUCOMISH xmm, m16 VUCOMISH_XMMf16_MEMf16_AVX512EVEX.LIG.NP.MAP5.W0 2E /rAVX10.1 or AVX512_FP16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_FP16_SCALAR

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.