VUCOMISS instruction (AVX, AVX10.1)

VUCOMISS is the VEX and EVEX form of UCOMISS, the quiet compare of two low singles into ZF, PF and CF that signals invalid only for a signaling NaN. UCOMISS’s page covers its uses and COMISS’s the reading of the flags; VCOMISS covers what the newer encodings add to a compare that writes no register: XMM16 to XMM31 and {sae} in the EVEX form (AVX512F or AVX10.1), no write mask, and VEX.L ignored. The VEX form needs AVX. Intel’s UCOMISS entry gives its warning against VEX.L = 1 under the name VCOMISS, as its UCOMISD entry does under VCOMISD.

Recorded on Zen 5

{evex} vucomiss xmm17, dword ptr [mem], a signaling NaN against 1.0 under FFC0H, gave unordered and set IE.
vucomiss xmm7, xmm11 compared the largest denormal, 007FFFFFh, with the smallest normal, 00800000h, under 3FC0H: less, CF alone, and no DE, since DAZ reads the denormal as zero; UCOMISS’s page shows a denormal setting DE when DAZ is clear.
vucomiss xmm1, dword ptr [mem] found +infinity equal to +infinity, ZF alone.

In compiled code

In our builds at -O2 with -march=x86-64-v3 or -v4, Clang 23 compiles a < b and a <= b on floats to vucomiss xmm1, xmm0 with SETA or SETAE, and GCC 14 uses VUCOMISS for isless() and ==, where it compiles < to VCOMISS. Clang tests == with VUCOMISS, JNE and JP only in a branch: for a value it emits VCMPEQSS, VMOVD and an AND at -v3, and at -v4 VCMPSS into K0 and KMOVW. GCC compiles _mm_comi_round_ss with a quiet predicate, such as _CMP_LT_OQ, to VUCOMISS, with {sae} for _MM_FROUND_NO_EXC.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows two macro-ops on pipes FP2/FP3 and FP4/FP5, two per cycle, as for UCOMISS. VUCOMISD is the double form.

Forms

Every encoding of VUCOMISS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VUCOMISS xmm, m32` VUCOMISS_XMMdq_MEMd	`VEX.LIG.NP.0F.WIG 2E /r`	AVX
`VUCOMISS xmm, xmm` VUCOMISS_XMMdq_XMMd	`VEX.LIG.NP.0F.WIG 2E /r`	AVX
`VUCOMISS xmm, xmm, {sae}` VUCOMISS_XMMf32_XMMf32_AVX512	`EVEX.LIG.NP.0F.W0 2E /r`	AVX10.1 or AVX512F
`VUCOMISS xmm, m32` VUCOMISS_XMMf32_MEMf32_AVX512	`EVEX.LIG.NP.0F.W0 2E /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, m32`	`xmm, xmm` `xmm, xmm, {sae}`
Sandy Bridge	8 / 1p01	2 / 1p01
Haswell, Broadwell	8 / 1p1	3 / 1p1
Skylake, Skylake-SP, Ice Lake	7 / 1p0	2 / 1p0
Alder Lake, Sapphire Rapids	8 / 1p0	3 / 1p0
Lunar Lake	9 / 2V0 V1	3 / 1.5V0 V1
Piledriver	6 / 1.5EX0 FPFMA FPU0	1 / 1EX0 FPFMA FPU0
Zen, Zen 2	10 / 1FPU0 FPU1 FPU2	3 / 1FPU0 FPU1 FPU2
Zen 3, Zen 4	11 / 1FP0 FP1	4 / 1FP0 FP1
Jaguar	8 / 1ALU0 FPA FPU0	3 / 1ALU0 FPA FPU0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low singles of the two sources are compared, and the result sets ZF, PF and CF.

The flags come from single 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = ucomi(xmm1.f32[0], src2.f32[0])  # 0 >, 1 <, 2 =, 3 unordered
zf = x in (2, 3)
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0
# only an SNaN raises IE
# {sae}: no exception flags

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VUCOMISS xmm, xmm/m32` `VUCOMISS xmm, xmm/m32, {sae}`
`xmm`	explicit	read
`xmm/m32`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
VEX forms
0	0	M	0	M	M
EVEX forms
0	0	M	0	M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-3
EVEX forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VUCOMISS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_ucomieq_ss` `int _mm_ucomieq_ss(__m128 __a, __m128 __b)`	`VUCOMISS xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_ucomige_ss` `int _mm_ucomige_ss(__m128 __a, __m128 __b)`	`VUCOMISS xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_ucomigt_ss` `int _mm_ucomigt_ss(__m128 __a, __m128 __b)`	`VUCOMISS xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_ucomile_ss` `int _mm_ucomile_ss(__m128 __a, __m128 __b)`	`VUCOMISS xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_ucomilt_ss` `int _mm_ucomilt_ss(__m128 __a, __m128 __b)`	`VUCOMISS xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_ucomineq_ss` `int _mm_ucomineq_ss(__m128 __a, __m128 __b)`	`VUCOMISS xmm, xmm` VEX.LIG -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512F_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Recorded on Zen 5#

In compiled code#