VUCOMXSD instruction (AVX10.2)

VUCOMXSD is the quiet partner of VCOMXSD: it compares the low doubles of a register and a register or eight bytes of memory and sets OF, SF, ZF, PF and CF in the same four patterns, which that page tabulates, but raises the invalid-operation exception only for a signaling NaN. It relates to VUCOMISD as VCOMXSD to VCOMISD: same opcode, 2Eh in map 0F with W1, with an F2 prefix in place of 66, and EVEX only, in AVX10.2. In the AVX10.2 specification (revision 7.0) the two instructions share their operation text word for word, an “ordered compare” for both; the difference in exceptions is stated only in the descriptions.

Equality in one test

C’s == is a quiet compare that must be false when either operand is a NaN. VUCOMISD sets ZF for an unordered result as well as for “equal”, so a compiler has to test PF too; VUCOMXSD clears ZF for unordered inputs, and ZF alone answers.

In our builds

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles return a == b; on doubles to VUCOMXSD and SETE, a != b to VUCOMXSD and SETNE, and if (a == b) choosing between two values to VUCOMXSD and one CMOVNE, where -march=x86-64-v4 needs VUCOMISD, CMOVNE and CMOVP. a < b, a <= b and a > b still use VUCOMISD with SETA or SETAE, the operands swapped for the first two. _mm_ucomieq_sd and _mm_ucomineq_sd give VUCOMXSD with SETE and SETNE. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Every encoding of VUCOMXSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VUCOMXSD xmm, xmm, {sae}` VUCOMXSD_XMMf64_XMMf64_AVX512	`EVEX.LIG.F2.0F.W1 2E /r`	AVX10.2
`VUCOMXSD xmm, m64` VUCOMXSD_XMMf64_MEMf64_AVX512	`EVEX.LIG.F2.0F.W1 2E /r`	AVX10.2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low doubles of the two sources are compared, and the result sets ZF, PF and CF.

The flags come from double 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = ucomx(xmm1.f64[0], src2.f64[0])  # 0 >, 1 <, 2 =, 3 unordered
of = x != 0
sf = x in (2, 3)
zf = x == 2
pf = x == 3
cf = x in (1, 3)
af = 0
# only an SNaN raises IE
# {sae}: no exception flags

Not run on a processor: none of these processors has AVX10.2.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VUCOMXSD xmm, xmm/m64, {sae}`
`xmm`	explicit	read
`xmm/m64`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX512_COM_EF_SCALAR` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Equality in one test#

In our builds#