VUCOMXSH instruction (AVX10.2)

VUCOMXSH compares the low half-precision values of a register and a register or two bytes of memory and sets OF, SF, ZF, PF and CF in the four patterns that VCOMXSD’s page tabulates. It raises the invalid-operation exception only for a signaling NaN, where VCOMXSH does so for any NaN. It extends VUCOMISH as VUCOMXSS extends VUCOMISS: opcode 2Eh in EVEX map 5, with an F3 prefix where VUCOMISH has none, part of AVX10.2. Like the other half-precision compares it takes {sae} to suppress the exception.

Equality on halves

An unordered result clears ZF, so ZF alone answers C’s ==. Clang 23 with -mavx10.2 compiles return a == b; on two _Float16 values to VUCOMXSH and SETE, and a < b to VUCOMISH with the operands swapped and SETA, as for floats and doubles. The intrinsics take another path: _mm_ucomieq_sh and _mm_ucomineq_sh become VCMPSH into a mask register, read back with KMOVW, rather than VUCOMXSH.

Availability

GCC 14 has no AVX10.2 option, so these builds are Clang’s alone. The AVX10.2 specification’s entry (revision 7.0) describes VUCOMXSH as differing from “VCOMISH” where VUCOMISH is meant, the counterpart of a slip in VCOMXSH’s entry. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Every encoding of VUCOMXSH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VUCOMXSH xmm, xmm, {sae}` VUCOMXSH_XMMf16_XMMf16_AVX512	`EVEX.LIG.F3.MAP5.W0 2E /r`	AVX10.2
`VUCOMXSH xmm, m16` VUCOMXSH_XMMf16_MEMf16_AVX512	`EVEX.LIG.F3.MAP5.W0 2E /r`	AVX10.2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low halves of the two sources are compared, and the result sets ZF, PF and CF.

The flags come from half 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = ucomx(xmm1.f16[0], src2.f16[0])  # 0 >, 1 <, 2 =, 3 unordered
of = x != 0
sf = x in (2, 3)
zf = x == 2
pf = x == 3
cf = x in (1, 3)
af = 0
# only an SNaN raises IE
# {sae}: no exception flags

Not run on a processor: none of these processors has AVX10.2.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VUCOMXSH xmm, xmm/m16, {sae}`
`xmm`	explicit	read
`xmm/m16`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX512_COM_EF_SCALAR` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Equality on halves#

Availability#