VUCOMXSS instruction (AVX10.2)

VUCOMXSS compares the low singles of a register and a register or four bytes of memory and sets OF, SF, ZF, PF and CF so that every relation, less than included, is one condition code, as VCOMXSS’s page lists. It differs from VCOMXSS only in raising the invalid-operation exception for signaling NaNs alone, as VUCOMISS does, and is to VUCOMISS what VCOMXSS is to VCOMISS: opcode 2Eh in map 0F with W0, an F3 prefix in place of none, and EVEX only, in AVX10.2. The flag pattern of each outcome is tabulated on VCOMXSD’s page, and VUCOMXSD is the double-precision version.

Where compilers use it

An unordered result clears ZF here, so the zero flag alone tells “equal” from everything else, NaN inputs included. That is what C’s == and != need, and the two operators are where Clang 23 uses VUCOMXSS: with -mavx10.2 it compiles return a == b; on floats to VUCOMXSS and SETE, where -march=x86-64-v4 gives a VCMPEQSS into a mask register read back with KMOVW. Relations such as a < b keep VUCOMISS. The intrinsic _mm_ucomieq_ss also gives VUCOMXSS, and _mm_comieq_ss gives VCOMXSS.

Availability

GCC 14 has no AVX10.2 option, so these builds are Clang’s alone. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Every encoding of VUCOMXSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VUCOMXSS xmm, xmm, {sae}` VUCOMXSS_XMMf32_XMMf32_AVX512	`EVEX.LIG.F3.0F.W0 2E /r`	AVX10.2
`VUCOMXSS xmm, m32` VUCOMXSS_XMMf32_MEMf32_AVX512	`EVEX.LIG.F3.0F.W0 2E /r`	AVX10.2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low singles of the two sources are compared, and the result sets ZF, PF and CF.

The flags come from single 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = ucomx(xmm1.f32[0], src2.f32[0])  # 0 >, 1 <, 2 =, 3 unordered
of = x != 0
sf = x in (2, 3)
zf = x == 2
pf = x == 3
cf = x in (1, 3)
af = 0
# only an SNaN raises IE
# {sae}: no exception flags

Not run on a processor: none of these processors has AVX10.2.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VUCOMXSS xmm, xmm/m32, {sae}`
`xmm`	explicit	read
`xmm/m32`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX512_COM_EF_SCALAR` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Where compilers use it#

Availability#