x86-64.net

Instruction

VUCOMXSS

Compares the low single-precision values of two operands like VCOMXSS but signals an invalid exception only for signaling NaNs.

Extensions
Forms
2 (2 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VUCOMXSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VUCOMXSS xmm, xmm, {sae} VUCOMXSS_XMMf32_XMMf32_AVX512EVEX.LIG.F3.0F.W0 2E /rAVX10.2
VUCOMXSS xmm, m32 VUCOMXSS_XMMf32_MEMf32_AVX512EVEX.LIG.F3.0F.W0 2E /rAVX10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_COM_EF_SCALAR

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.