x86-64.net

Instruction

VUNPACKB

Unpacks tightly packed 2- to 7-bit fields into bytes, zero- or sign-extended, with the field size and start given by an immediate.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VUNPACKB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VUNPACKB xmm {k}{z}, xmm, imm8 VUNPACKB_XMMu8_MASKmskw_XMMu8_IMM8_AVX512EVEX.128.NP.0F3A.W0 3D /r ibAVX10_V2_AUX + AVX10
VUNPACKB xmm {k}{z}, m128, imm8 VUNPACKB_XMMu8_MASKmskw_MEMu8_IMM8_AVX512EVEX.128.NP.0F3A.W0 3D /r ibAVX10_V2_AUX + AVX10
VUNPACKB ymm {k}{z}, ymm, imm8 VUNPACKB_YMMu8_MASKmskw_YMMu8_IMM8_AVX512EVEX.256.NP.0F3A.W0 3D /r ibAVX10_V2_AUX + AVX10
VUNPACKB ymm {k}{z}, m256, imm8 VUNPACKB_YMMu8_MASKmskw_MEMu8_IMM8_AVX512EVEX.256.NP.0F3A.W0 3D /r ibAVX10_V2_AUX + AVX10
VUNPACKB zmm {k}{z}, zmm, imm8 VUNPACKB_ZMMu8_MASKmskw_ZMMu8_IMM8_AVX512EVEX.512.NP.0F3A.W0 3D /r ibAVX10_V2_AUX + AVX10
VUNPACKB zmm {k}{z}, m512, imm8 VUNPACKB_ZMMu8_MASKmskw_MEMu8_IMM8_AVX512EVEX.512.NP.0F3A.W0 3D /r ibAVX10_V2_AUX + AVX10

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX10_V2_AUX_128

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None yet: XED lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_256

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None yet: XED lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_512

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None yet: XED lists these instructions only under its placeholder for future processors.

More AVX10_V2_AUX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.