VUNPACKB

VUNPACKB spreads fields of 2 to 7 bits, packed from bit 0 of its source with no gaps, into the bytes of its destination, one field to a byte, zero-extended or sign-extended. An xmm, ymm or zmm register gets 16, 32 or 64 fields from a register or memory operand of its own size, under a write mask of one bit per byte. It belongs to AVX10_V2_AUX of the ACE specification: opcode 3Dh with no prefix in map 0F3A, W0, with an immediate. It is the way back from narrow integers stored densely, such as 4-bit or 2-bit weights, to bytes that byte instructions such as VPDPBSSD can use.

The immediate#

Bits 4:2 give the field size n, bit 5 asks for sign extension, and bits 1:0 pick which run of fields to take. One run of 64 fields of 4 bits fills only half of a zmm register, so a register of 4-bit data holds two runs, and of 2-bit data four: with a start value s, byte i takes the field at bit (s × VL/8 + i) × n. One load can feed two or four VUNPACKB, the point of the start field in the ACE specification. Sizes 3 and 4 allow starts 0 and 1, and sizes 5 to 7 start 0 only.

So 31h (size 4, start 1, signed) on a zmm register sign-extends the nibbles in bits 511:256, and 14h on an xmm register takes 16 fields of 5 bits from the low 80 bits, zero-extended.

Nothing faults#

Bits 7:6 are reserved, and so are the size codes 0 and 1 and the start values that a size does not allow, but no immediate raises #UD: the specification’s pseudocode treats sizes 0 and 1 as 2, lowers a start of 2 or 3 to 1 for sizes 3 and 4, and ignores the start for larger sizes, as the Operation section does. The memory operand is read whole whatever the mask, as its exception class E4NF says.

In our builds and on Zen 5#

Clang 23’s assembler and GNU as 2.44 reject the mnemonic, and ACE’s _mm512_unpackb is missing from Clang 23’s headers. On the Zen 5 behind this site’s recorded cases, whose CPUID reports no AVX10, all six forms raised #UD.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)                    # CPUID: no AVX10
if not cpuid_leaf(0x24, 1)[2] >> 3 & 1:
    fault(UD)                    # CPUID: no AVX10_V2_AUX
x = src2.read()                  # whole, whatever the mask (E4NF)
n = max(imm8 >> 2 & 7, 2)        # bits a field: imm8[4:2], 2 to
                                 # 7; 0 and 1 count as 2
s = imm8 & 3                     # the run: 0 to 3 for 2 bits, 0 or
if n > 4:                        # 1 for 3 and 4 bits, 0 above
    s = 0
elif n > 2:
    s = min(s, 1)
for i in range(VL // 8):         # field i into byte i
    if k1[i]:                    # 1 without a write mask
        j = (s * VL // 8 + i) * n
        f = x >> j & (1 << n) - 1
        if imm8 >> 5 & 1 and f >> n - 1:
            f |= 0xFF << n       # imm8[5]: sign-extended
        zmm1.b[i] = f
    elif zeroing:
        zmm1.b[i] = 0
    # else: the byte keeps its value
# imm8[7:6] are reserved and ignored: no encoding of imm8 faults
# zmm1 is zeroed from bit VL up. Zen 5, with AVX-512 but not
# AVX10.2, raises #UD for every form

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10_V2_AUX instructions

• VCVTBF42HF8
• VCVTBF62HF8
• VCVTBF82BF4S
• VCVTBF82BF6S
• VCVTBF82PS
• VCVTBIASPS2BF8
• VCVTBIASPS2BF8S
• VCVTBIASPS2HF8
• VCVTBIASPS2HF8S
• VCVTHF62HF8
• VCVTHF82BF4S
• VCVTHF82HF6S
• VCVTHF82PS
• VCVTPS2BF8
• VCVTPS2BF8S
• VCVTPS2HF8
• VCVTPS2HF8S
• VCVTROPS2HF8
• VCVTROPS2HF8S
• VPMOVSSDB