VUNPCKHPD

VUNPCKHPD pairs the high doubles of two sources, a1 and b1, as UNPCKHPD does, whose page shows how SSE2 code uses it to bring element 1 down for horizontal work. The VEX and EVEX forms add a separate destination, memory at any alignment and zeroing above the vector length; the ymm and zmm forms work in each 128-bit lane, so a ymm result is (a1, b1, a3, b3). VUNPCKLPD explains the lanes, the encodings and the masking and broadcast of the EVEX forms. Zen 5’s recorded cases:

• vunpckhpd ymm0, ymm13, ymmword ptr [mem] gave double 1 of YMM13 and of memory in the low lane and double 3 of each in the high lane, reading bytes 8 to 15 and 24 to 31 of memory.
• vunpckhpd ymm5{k2}{z}, ymm5, ymm5, one register as both sources, wrote double 1 of YMM5 into element 0 and double 3 into element 3, the two that k2 selects, and zeroed elements 1 and 2.
• vunpckhpd xmm17{k1}{z}, xmm30, qword bcst [mem], with bits 1:0 of K1 clear, zeroed all of ZMM17.

The copy that stays#

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, v[0] + v[1] on a __m128d shows the compilers apart. GCC 14 still copies v with VMOVAPD before vunpckhpd xmm0, xmm0, xmm0 and VADDSD, the sequence of the legacy form, though the VEX form could write the high double to another register; Clang 23 emits vshufpd xmm1, xmm0, xmm0, 1 and VADDSD, two instructions. Clang also compiles _mm_movehl_ps(a, b) to vunpckhpd xmm0, xmm1, xmm0, as VMOVHLPS’s page notes. In the loops that split complex doubles into two arrays, VUNPCKHPD takes the imaginary parts beside VUNPCKLPD in both compilers at -v3.

AMD’s latency spreadsheet for Zen 5 lists the VEX and the EVEX rows like VUNPCKLPD’s: one macro-op of 1 cycle, four per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    j = i - i % 2 + i % 2 // 2 + 1  # in the lane of i
    if k1[i]:                       # 1 without a write mask
        if i % 2 == 0:
            zmm1.q[i] = zmm2.q[j]
        else:
            zmm1.q[i] = src3.q[j]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VUNPCKHPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions