VUNPCKHPS

VUNPCKHPS interleaves the high singles of two sources, (a2, b2, a3, b3), the VEX and EVEX form of UNPCKHPS, whose page shows how compilers use it to bring the upper half down. It adds a separate destination, memory at any alignment and zeroing above the vector length; the ymm and zmm forms work in each 128-bit lane, so the ymm form gives (a2, b2, a3, b3, a6, b6, a7, b7), and the memory form reads bytes 8 to 15 of each 16. VUNPCKLPS explains the lanes, the encodings and the code that pairs the two. The VEX forms need AVX, the EVEX forms AVX-512F (with AVX512VL below 512 bits) or AVX10.1, which add masking and a broadcast single.

Zen 5’s recorded cases:

• vunpckhps ymm0, ymm13, ymmword ptr [mem] filled the low lane from elements 2 and 3 of YMM13 and of memory, and the high lane from elements 6 and 7.
• vunpckhps ymm5{k6}{z}, ymm5, ymm5, one register as both sources, doubled each high single of a lane but wrote only elements 2, 5 and 7, which k6 selects: the copies of elements 3, 6 and 7. The other five were zeroed.
• vunpckhps xmm5{k7}{z}, xmm5, dword bcst [mem] wrote element 2 of XMM5 and the single from memory into elements 0 and 1 and zeroed 2 and 3, k7’s clear bits.

In compiled code#

In our builds at -O2 with -march=x86-64-v3, the loops that interleave two float arrays use VUNPCKHPS for the upper pairs of each lane beside VUNPCKLPS, in GCC 14 and Clang 23 alike. For the total of a __m256 kept in C’s order, GCC takes element 2 of each half with vunpckhps xmm, xmm, xmm of one register and Clang uses VSHUFPD. _mm256_unpackhi_ps is one VUNPCKHPS.

AMD’s latency spreadsheet for Zen 5 lists it like VUNPCKLPS: one macro-op of 1 cycle, four per cycle, in the VEX and the EVEX rows.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    j = i - i % 4 + i % 4 // 2 + 2  # in the lane of i
    if k1[i]:                       # 1 without a write mask
        if i % 2 == 0:
            zmm1.d[i] = zmm2.d[j]
        else:
            zmm1.d[i] = src3.d[j]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VUNPCKHPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions