VUNPCKLPD

VUNPCKLPD pairs the low doubles of two sources, as UNPCKLPD does, whose page shows the broadcasts and pairs that baseline code builds with it. The VEX and EVEX forms add a separate destination, memory at any alignment and zeroing above the vector length. The ymm and zmm forms pair within each 128-bit lane: from a and b a ymm result is (a0, b0, a2, b2), so doubles 1 and 3 of each source are left out, and the memory form reads 32 bytes of which it uses bytes 0 to 7 and 16 to 23. The VEX forms need AVX, ymm included; the EVEX forms (AVX-512F, with AVX512VL below 512 bits, or AVX10.1) add a write mask per double and a broadcast double as the second source. VUNPCKHPD takes the high doubles. Zen 5’s recorded cases:

• vunpcklpd ymm7, ymm11, ymmword ptr [mem] gave double 0 of YMM11 and of memory in the low lane and double 2 of each in the high lane.
• vunpcklpd ymm17{k4}{z}, ymm30, ymm2, with k4’s low bits 0101b, wrote doubles 0 and 2 of YMM30 into elements 0 and 2 and zeroed the elements that would have come from YMM2.
• vunpcklpd ymm24{k2}, ymm3, ymmword ptr [mem], with 1001b, wrote element 0 from YMM3 and element 3 from memory and kept 1 and 2.

Two arrays from one#

In our builds at -O2, splitting an array of complex doubles, a global array of structs, into real and imaginary arrays shows the lanes at work. With -march=x86-64-v3, GCC 14 loads two ymm registers, pairs them with VUNPCKLPD and VUNPCKHPD, and puts each result in order with vpermpd ymm, ymm, 0xd8; Clang 23 rearranges the 128-bit halves first, with VPERM2F128 and VINSERTF128, so that the unpacks need no fix-up. With -march=x86-64-v4 GCC uses VPERMT2PD on zmm registers instead, while Clang stays on ymm registers, with two VPERM2F128 before the unpacks. On xmm registers Clang prefers VMOVLHPS for _mm_unpacklo_pd; the ymm intrinsic is VUNPCKLPD in both.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows one macro-op on pipes FP0 to FP3, a latency of 1 cycle and four per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    j = i - i % 2 + i % 2 // 2  # in the lane of i
    if k1[i]:                   # 1 without a write mask
        if i % 2 == 0:
            zmm1.q[i] = zmm2.q[j]
        else:
            zmm1.q[i] = src3.q[j]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VUNPCKLPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPS
• VXORPD
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions