VUNPCKLPS

VUNPCKLPS interleaves the low singles of two sources, as UNPCKLPS does, whose page shows the pattern and how compilers build vectors with it. The newer encodings add a separate destination, a memory operand at any alignment and zeroing above the vector length. The ymm and zmm forms interleave within each 128-bit lane: from a and b they give (a0, b0, a1, b1) and then (a4, b4, a5, b5), so the singles 2, 3, 6 and 7 of each source are left out, not the upper half of the register. The VEX forms need AVX, ymm included; the EVEX forms (AVX-512F, with AVX512VL below 512 bits, or AVX10.1) add a write mask per single and a broadcast second source. VUNPCKHPS takes the high singles of each lane.

Zen 5’s recorded vunpcklps ymm7, ymm11, ymm7 placed elements 0 and 1 of YMM11 and YMM7 alternately in the low lane and elements 4 and 5 in the high lane. With a broadcast source, vunpcklps zmm24{k4}, zmm3, dword bcst [mem] interleaved ZMM3’s low singles of each lane with the single from memory: the selected odd positions, 5, 7, 11 and 13, got the memory value, the selected even ones ZMM3’s elements, and the six positions k4 leaves clear kept their values.

Interleaving two arrays#

In our builds at -O2 with -march=x86-64-v3, GCC 14 and Clang 23 merge two global float arrays into one of (x, y) pairs with a VUNPCKLPS and a VUNPCKHPS of the same two vectors, which leaves the pairs of each half in the wrong lanes, and two lane moves, VINSERTF128 and VPERM2F128, to put them in order. With -march=x86-64-v4, GCC uses two VPERMT2PS on zmm registers, and Clang loads the x values zero-extended into quadwords with VPMOVZXDQ and fills the gaps with VPERMT2PS on ymm. _mm512_mask_unpacklo_ps is one masked VUNPCKLPS in both.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows the same entry: one macro-op, a latency of 1 cycle, four per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    j = i - i % 4 + i % 4 // 2  # in the lane of i
    if k1[i]:                   # 1 without a write mask
        if i % 2 == 0:
            zmm1.d[i] = zmm2.d[j]
        else:
            zmm1.d[i] = src3.d[j]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VUNPCKLPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VXORPD
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VXORPD
• VXORPS

All 686 AVX10.1 instructions