VXORPD

VXORPD is the bitwise exclusive OR of two vectors, read as 64-bit elements: VXORPS with another element size. The XORPS and VXORPS pages cover its uses, zeroing a register and flipping signs, and what a write mask does to an XOR of a register with itself. The bits of the result are the same in both forms; the element size counts only for the EVEX form’s write mask and its broadcast of one 64-bit value, and that form needs AVX512DQ (AVX512F alone has the integer VPXORQ).

The same code, two spellings#

GCC 14 and Clang 23 at -O2 write the same operations on doubles with different instructions:

• _mm256_setzero_pd() is vxorpd xmm0, xmm0, xmm0 in GCC and VXORPS in Clang. Both zero only xmm0 in the source, since a VEX instruction clears the bits above its result: the case recorded on Zen 5 with vxorpd xmm0, xmm13, xmm9 left bits 128 to 511 of zmm0 zero.
• -b[i] over an array of doubles, with -march=x86-64-v3, is VXORPD with a broadcast -0.0 in GCC and VXORPS with the same constant in Clang; with -march=x86-64-v4, GCC uses VXORPD on zmm registers.

Neither choice changes the result, and AMD’s Zen 5 guide lists both forms alike, with a latency of 1 cycle on all four vector pipes.

Bits, not numbers#

Because the operation sees only bits, Zen 5’s recorded cases show what an arithmetic instruction would not do. vxorpd ymm12, ymm6, ymmword ptr [mem] turned two denormals, 15 and 1 times 2^-1074 as bit patterns, into 14 times 2^-1074, and 16 and 1 into 17, with MXCSR untouched; a NaN whose bits were all ones, XORed with the smallest denormal, became another NaN with the last bit clear. A sign flip by XOR with -0.0 is therefore exact for every input, NaNs included, which is why compilers use it for negation instead of a subtraction from zero (see VSUBPS).

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = zmm2.q[i] ^ src3.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VXORPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPS

All 686 AVX10.1 instructions