VXORPS

VXORPS is XORPS in VEX and EVEX encodings: a bitwise exclusive OR that leaves MXCSR alone. The XORPS page covers its two everyday jobs, zeroing a register and flipping signs; the VEX form adds a separate destination, 256 bits and a memory operand at any alignment, and the EVEX form, which needs AVX512DQ (AVX512F alone has VPXORD), adds masking and a broadcast single. GCC 14 negates doubles with VXORPD and Clang 23 with VXORPS: the bits are the same.

Under a mask#

Masking changes what XOR with itself means. In the cases recorded on Zen 5:

• vxorps xmm12, xmm6, xmm6 cleared all 512 bits of zmm12, as a VEX instruction clears the bits above its result.
• vxorps zmm24{k2}, zmm3, zmm3 zeroed only the elements whose mask bit was set; the others kept what zmm24 held before, so the old value of the destination is an input.
• vxorps ymm5{k7}{z}, ymm5, ymm5 gave zeros everywhere, the selected elements from the XOR and the others from the zeroing.

A conditional sign flip#

For a[i] = c[i] < 0.0f ? -b[i] : b[i], GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 flip every sign with VXORPS and -0.0, compare with VCMPLTPS, and pick between the two with VBLENDVPS. With -march=x86-64-v4 the compare writes a mask register, and the two compilers use it differently: Clang applies one merge-masked vxorps ymm2{k1}, ymm2, ymm1 that flips only the selected elements in place, while GCC flips all of them into another zmm register and copies the selected ones back with a masked VMOVAPS.

In the optimization guide

What the optimization guide says about VXORPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Zeroing and dependency-breaking idioms: The vector registers have idioms of their own: pxor, xorps, xorpd, pandn, andnps, the integer subtractions psub and the comparisons pcmpgt of a register with itself, with their VEX and EVEX forms, which Intel counts for 512-bit registers only unmasked. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = zmm2.d[i] ^ src3.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VXORPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD

All 686 AVX10.1 instructions