VZEROALL instruction (AVX)

VZEROALL sets vector registers 0 to 15 to zero, whole: XMM, YMM and, on processors with AVX-512, the full ZMM register. Outside 64-bit mode only registers 0 to 7 exist and are cleared. It has no operands and changes no flags; MXCSR is left alone. It shares opcode 0F 77 with VZEROUPPER, told apart by VEX.L (1 here, 0 there), and with EMMS, which has no VEX prefix.

What it leaves

The SDM states that ZMM16 to ZMM31 keep their values, and says nothing about the mask registers. AMD’s manual, in the edition we cite, describes it for YMM registers only. Zen 5 agrees with Intel’s text: its one recorded case cleared all 512 bits of ZMM0 to ZMM15, which started with nonzero values, and changed nothing in ZMM16 to ZMM31, K0 to K7 or MXCSR.

Compared with VZEROUPPER

VZEROUPPER, whose page covers the cost of mixing AVX and SSE code, clears only bits 128 and up and is what compilers emit before calls and returns. VZEROALL also clears the low halves. Both leave the upper state clean, and Intel’s optimization manual draws them as the same transition in its diagrams of the AVX and SSE states (Figures 15-1 and 15-2, Section 15.3), but VZEROALL destroys every value in the sixteen registers, including the arguments and results of the vector calling conventions. GCC 14 and Clang 23 compile _mm256_zeroall() to it, but put VZEROUPPER at the end of functions that used the upper halves.

It is also the slower of the two on Zen 5: AMD’s latency spreadsheet lists VZEROUPPER as one macro-op, but VZEROALL as microcoded. Where only the upper state needs to be clean, VZEROUPPER is the instruction to use.

Forms

Every encoding of VZEROALL that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VZEROALL` VZEROALL	`VEX.256.NP.0F.WIG 77`	AVX

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(16):
    zmm[i] = 0

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-8

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VZEROALL, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm256_zeroall` `void _mm256_zeroall(void)`	`VZEROALL` VEX.256 -mavx

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

What it leaves#

Compared with VZEROUPPER#