WBINVD

WBINVD writes every modified line of this processor’s caches back to memory, then empties them, and signals the caches above it to do the same. It is the whole-cache counterpart of CLFLUSH, which a program at any privilege level can use on one line: WBINVD runs only at CPL 0, and it is an operating system’s or firmware’s tool for the moments when no cached copy may survive, such as a change of memory types.

Where it is needed#

Intel’s Volume 3 uses WBINVD in its procedure for changing the MTRRs on a multiprocessor system: each processor disables interrupts, sets CR0.CD to stop filling the caches, flushes them with WBINVD, flushes its TLBs, changes the MTRRs and flushes again before caching resumes. With self-snooping (CPUID leaf 1, EDX bit 27) the first flush may be unnecessary, except for changes such as write-back memory becoming uncached for memory-mapped I/O.

What it reaches#

• Caches shared with this processor, at every level, are written back and emptied. Intel’s Volume 3 adds that caches this processor does not share, such as other cores’ own, may not be. AMD’s manual leaves it to CPUID: where bit 0 of EDX in leaf 8000_001DH is clear for a cache level, the lower caches of other processors that share that level are flushed too.
• Not the TLBs, AMD’s manual says.
• The time grows with the size of the caches, which both manuals warn can delay interrupts. AMD’s processors may support EFER.INTWB (CPUID 8000_0008H, EBX bit 13), which lets an interrupt stop the flush; it then starts over after the return.

Both vendors list WBINVD as serializing. INVD empties the caches without writing anything back, losing modified data, and WBNOINVD (F3 0F 09) writes back without emptying, leaving the lines in place; on processors without WBNOINVD, that encoding runs as WBINVD.

Running it#

At CPL 3 it raises #GP(0); Zen 5 did so in both recorded cases. Under VMX, the WBINVD exiting control makes it, and WBNOINVD, exit to the hypervisor. GCC 14 and Clang 23 provide _wbinvd(), which compiles to the one instruction at -O2 with no option. AMD’s Zen 5 guide lists WBINVD as microcoded.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0:
    fault(GP, 0)
pass                             # writes every modified line of the
                                 # caches back to memory, drops them
                                 # all, and tells the external caches
                                 # to do the same; it may take long
# AMD: whether caches that other processors share are flushed too
# is in CPUID 8000_001DH, EDX[0] of each level

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

privileged: CPL 0 only; may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to WBINVD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More System instructions

• ARPL
• CLTS
• HLT
• INVD
• INVLPG
• LAR
• LGDT
• LIDT
• LLDT
• LMSW
• LSL
• LTR
• RDMSR
• RDPMC
• RDTSC
• RSM
• SGDT
• SIDT
• SLDT
• SMSW
• STR
• SWAPGS
• VERR
• VERW
• WRMSR