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Instruction

WRMSRLIST

Writes up to 64 model-specific registers from a table in memory to the addresses listed in a second table, selected by a bit mask in RCX.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of WRMSRLIST that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
WRMSRLIST 64-bit mode only WRMSRLISTF3 0F 01 C6MSRLIST

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
MSRLIST

MSRLIST
CPUID.(EAX=07H,ECX=1):EAX[27] MSRLIST

Panther Lake, Nova Lake, Diamond Rapids, Sierra Forest, Clearwater Forest

More MSRLIST instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.