WRPKRU

WRPKRU loads EAX into PKRU, the register of protection keys for user pages. The page tables tag each user page with one of 16 keys, and PKRU gives each key k two bits: bit 2k denies every data access to its pages, bit 2k + 1 denies writes. One unprivileged instruction thus changes the rights of every page of a key, for the running thread alone, without a system call or a TLB flush. ECX and EDX must be 0, or WRPKRU raises #GP; it raises #UD unless the kernel has set CR4.PKE, which CPUID leaf 7, ECX bit 4 (OSPKE) reports. Bits 63:32 of RAX, RCX and RDX do not count: on Zen 5, EAX = FFFFFFFCH under random upper bits became PKRU as it was, and ECX or EDX of 1 raised #GP and left PKRU alone.

Keys under Linux#

Linux 7.3 starts a process with PKRU at 55555554H (its init_pkru_value): key 0, which every page has until the program says otherwise, open, and keys 1 to 15 closed to all access. A program asks the kernel for a key with pkey_alloc() and tags pages with pkey_mprotect(); the kernel’s documentation describes glibc’s pkey_set(), which changes a key’s rights afterwards, as a wrapper around this write. An access that a key denies raises #PF, which Linux delivers as SIGSEGV with si_code SEGV_PKERR. Keys govern data accesses only: instruction fetches ignore them (Intel’s manual, volume 3), so a page can stay executable while unreadable.

A window around one access#

Opening a key, reading and closing it relies on their order. The manuals state it differently: Intel’s says WRPKRU never runs speculatively and that no access PKRU governs runs before earlier WRPKRUs have updated it; AMD’s says it orders the loads and stores before it against those after it. With -mpku, or an -march such as skylake-avx512 or znver3 (x86-64-v4 lacks it), GCC 14 and Clang 23 at -O2 compile _wrpkru(open); v = *p; _wrpkru(old); to the load between two WRPKRUs. Clang zeroes ECX and EDX before each; GCC zeroes them once.

Any code in the process can run WRPKRU, so keys stop stray pointers, not an attacker who chooses the instructions. RDPKRU reads the register. With an F3 prefix these bytes are STUI on Intel’s processors with user interrupts. AMD’s Zen 5 guide lists WRPKRU as microcoded.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if ecx != 0 or edx != 0:             # bits 63:32 of RCX and RDX do not
    fault(GP, 0)                     # count, nor those of RAX
pkru = eax
# Intel's manual allows no 66, F2 or F3 prefix here: with F3 the
# bytes are STUI on its processors with user interrupts

Operands

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More PKU instructions

• RDPKRU