Instruction
WRUSSD
Lets ring-0 code write a 32-bit value to a user-mode shadow stack.
- Extensions
- Forms
- 2 (1 Legacy, 1 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
WRUSSD m32, r32
WRUSSD_MEMu32_GPR32u32 | 66 0F 38 F5 /r | CET |
WRUSSD m32, r32
WRUSSD_MEMu32_GPR32u32_APX | EVEX.LLZ.66.MAP4.W0 65 /r | APX_F + CET |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to WRUSSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_wrussd
void _wrussd(unsigned int __a, void *__p) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
CET | CET | Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest |
APX_F_CET | APX_F + CET | Nova Lake, Diamond Rapids |
More APX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.