XBEGIN

XBEGIN starts a transaction of Intel’s Restricted Transactional Memory (RTM). Execution goes on with the next instruction, transactionally: the processor tracks every cache line the code reads and writes, and keeps its stores from other processors until XEND commits them all at once. If anything stops that (another processor touching a tracked line, too much data, some instructions and system events, or XABORT), the transaction aborts: the registers and memory go back to what they were at XBEGIN, and execution jumps to the fallback address, the operand of XBEGIN, with a status in EAX. Nothing guarantees that a transaction ever commits, so the fallback path has to do the work another way, usually under a lock.

The status in EAX#

After an abort, bit 0 means XABORT, with its 8-bit operand in bits 31 to 24; bit 1 that a retry may succeed; bit 2 a conflict with another processor; bit 3 a full buffer; bit 4 a #DB or #BP; bit 5 an abort in a nested transaction. EAX may also be 0. With -mrtm, GCC 14 at -O2 compiles _xbegin() to mov eax, -1 and an XBEGIN whose fallback is the very next instruction, so both paths meet at a cmp eax, -1: -1 is _XBEGIN_STARTED, what _xbegin() returns when the transaction runs. Clang 23 sends the fallback to a label of its own instead.

Inner XBEGINs only count the nesting; an abort returns to the outermost one’s fallback. With a 66 prefix the offset is 16 bits, but unlike a near JMP the target is not cut to 16 bits.

Where it runs#

XBEGIN, XEND and XABORT need CPUID.(EAX=7,ECX=0):EBX[11]; without it they raise #UD. Intel’s own documents say where RTM is gone or disabled:

• Microcode from Intel’s platform update 2021.1 and later disables TSX by default on 6th- to 10th-generation Core processors and the related Xeon E3 and E parts, as listed in Intel’s article: every XBEGIN aborts, CPUID may still report RTM, and CPUID.(EAX=7,ECX=0):EDX[11], RTM_ALWAYS_ABORT, says that this is so.
• The optimization manual says that the 12th-generation Core processors with P-cores and E-cores keep one instruction set on both kinds of core, and that their E-cores do not support TSX.

AMD’s manual defines no RTM instructions and marks the CPUID bits of RTM and HLE reserved. On this site’s Zen 5, all four cases, with 32- and 16-bit offsets, raised #UD.

In the optimization guide

What the optimization guide says about XBEGIN, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Haswell and Broadwell

• Transactional memory: A transaction tracks its data in the 8-way L1 data cache, so writing nine lines of one set aborts it.

Vulnerability mitigations

Mitigations of these processor vulnerabilities use XBEGIN:

• CVE-2019-11135: TSX Asynchronous Abort

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 0)[1] >> 11 & 1:
    fault(UD)                    # CPUID: no RTM
room = rtm_nest < rtm_nest_max
if room and not ldtrk_suspended:
    if rtm_nest == 0:            # the outermost: one starts
        t = low(rip + signed(rel), 64)
                                 # rel16 or rel32, sign-extended; a
                                 # 66 prefix does not cut RIP to 16
                                 # bits here
        if not canonical(t):
            fault(GP, 0)
        fallback = t
        rtm_active = 1           # registers and memory as they are
                                 # now are what an abort restores
    rtm_nest = rtm_nest + 1
else:
    tx_abort(UNDEFINED)          # too deep, or inside a region of
                                 # XSUSLDTRK
# XBEGIN goes on with the next instruction: it is no branch until
# an abort, which needs no ENDBR64 at the fallback address

Operands

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to XBEGIN, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More RTM instructions

• XABORT
• XEND
• XTEST