x86-64.net

Instruction

XCHG

Swaps two operands; with a memory operand it is atomic even without a LOCK prefix.

Extensions
Forms
5 (5 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of XCHG that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
XCHG m8, r8 XCHG_MEMb_GPR886 /rBase instruction set
XCHG r8, r8 XCHG_GPR8_GPR886 /rBase instruction set
XCHG m16/32/64, r16/32/64 XCHG_MEMv_GPRv87 /rBase instruction set
XCHG r16/32/64, r16/32/64 XCHG_GPRv_GPRv87 /rBase instruction set
XCHG r16/32/64, rAX XCHG_GPRv_OrAX90+rBase instruction set

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.