XCHG

XCHG swaps two operands. Between registers that is all it does. With a memory operand it is also an atomic instruction: the processor locks the location for the read and the write as if a LOCK prefix were there, whether or not it is, so no other processor can change the value in between.

Uses of the lock#

• Atomic exchange. C11’s atomic_exchange on a long compiles to a MOV of the new value into RAX and xchg qword ptr [rip + g], rax, with GCC 14 and Clang 23 at -O2.
• Sequentially consistent stores. A locked instruction is never reordered with loads or stores before or after it, while plain MOVs let a load complete before an earlier store. Both compilers therefore compile a sequentially consistent atomic_store to XCHG and drop the old value (see MOV).
• Test-and-set locks. mov eax, 1 followed by xchg eax, [lock] takes a lock word and leaves in EAX whether it was already taken; test eax, eax and a branch retry while it was, with PAUSE in the waiting loop. Releasing such a lock is a plain store of 0.

XCHG always writes, and returns only the old value. An update that depends on that value, such as “store x only if the location still holds y”, needs CMPXCHG with LOCK; an atomic addition is XADD.

Split locks#

The lock covers any operand, aligned or not, but one that spans two cache lines cannot be locked within a cache: Intel’s and AMD’s manuals both make it a bus lock, which involves every processor of the system. Where the processor supports split-lock disable, system software can make such an access raise #AC(0) instead (Intel’s Volume 3A, Section 11.1.2.3).

The one-byte forms#

90+r swaps rAX with another register in one byte. The slot for rAX itself, 90, is NOP, and F3 90 is PAUSE; the Operation section below shows which register forms clear bits 63:32.

In the optimization guide

What the optimization guide says about XCHG, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Move elimination: A register-to-register copy can be made at renaming, by pointing the destination at the physical register of the source; the move then has no latency and uses no execution unit.

Zen and Zen+

• Integer execution: Register-to-register moves of 32-bit and 64-bit general registers and of XMM registers, and xchg of general registers, take no execution cycle, while a YMM move renames only its lower half and moves the upper one in a pipe. sources differ

Zen 2

• Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole XMM and YMM registers take no execution cycle, where Zen 1 moves the upper half of a YMM register in a pipe. sources differ

Zen 3

• Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole XMM and YMM registers take no execution cycle, nor do the zeroing idioms such as xor eax, eax and vpxor, which also break the dependency on the old value; sbb eax, eax depends only on the carry flag, and pcmpeqd xmm0, xmm0 sets all ones without waiting. sources differ

Zen 4

• Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole vector registers take no execution cycle, nor do the zeroing idioms such as xor eax, eax and vpxor, which also break the dependency on the old value; sbb eax, eax depends only on the carry flag. sources differ

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()                  # memory: one atomic read and write, with
b = src.read()                   # or without LOCK
dest.write(b)                    # 32-bit registers: bits 63:32 cleared in
src.write(a)                     # both, even for XCHG EAX, EAX (87 C0)
# the byte 90, which would be XCHG EAX, EAX, is NOP instead: it clears
# nothing (XCHG R8D, EAX, 41 90, does)

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

Memory forms

locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SAR
• SBB
• SCAS
• SETcc
• SHL
• SHLD
• SHR
• SHRD
• STC
• STD
• STI
• STOS
• SUB
• TEST
• UD0
• UD1
• UD2
• UDB
• XADD
• XLAT
• XOR

All 109 General-purpose instructions