Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

XEND ends an RTM transaction that XBEGIN started. At the outermost level it commits: every store of the transaction becomes visible to other processors at once, and a commit orders memory as a LOCK-prefixed instruction does, even for a transaction without memory operations. If the commit fails, the transaction aborts like any other: registers and memory return to their state at XBEGIN, and execution goes to XBEGIN’s fallback address with the status in EAX. An inner XEND only lowers the nesting count, which software cannot read; nothing commits until the count is back at zero.

Outside a transaction

XEND raises #GP(0) when no transaction is running. The fallback path is such a place: after an abort the code runs normally, so XEND belongs on the transactional path alone. In the usual shape, _xend() ends the branch taken when _xbegin() returned _XBEGIN_STARTED, and the other branch does the same work under a lock; GCC 14 and Clang 23 at -O2 with -mrtm keep that shape, with XEND right after the transactional work. A transaction that checks the lock is free, and calls _xabort if not, has the lock in its read set, so a thread that takes the lock on the fallback path aborts every transaction running at that moment.

XEND inside a region of XSUSLDTRK, which suspends the tracking of loads, aborts the transaction instead of committing it.

Availability

XEND needs RTM, CPUID.(EAX=7,ECX=0):EBX[11], like XBEGIN, whose page says where Intel disables it; without that bit it raises #UD. Where Intel’s microcode makes RTM always abort, XEND is never reached on the transactional path, since every XBEGIN goes straight to the fallback. AMD’s manual defines no XEND, and both of Zen 5’s cases raised #UD.

Forms

Every encoding of XEND that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
XEND XENDNP 0F 01 D5RTM

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
ModelXEND
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake, Sapphire Rapids100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 0)[1] >> 11 & 1:
    fault(UD)                    # CPUID: no RTM
if not rtm_active:
    fault(GP, 0)                 # no transaction to end
if ldtrk_suspended:
    tx_abort(UNDEFINED)          # inside a region of XSUSLDTRK
elif rtm_nest > 1:
    rtm_nest = rtm_nest - 1      # an inner one: nothing commits
elif tx_commit():                # the outermost: every store of the
    rtm_nest = 0                 # transaction visible at once,
    rtm_active = 0               # ordered as a LOCK instruction is
else:
    tx_abort(UNDEFINED)          # it could not commit

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no RTM, and every one raised an exception.

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to XEND, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_xend void _xend(void)

XEND Legacy -mrtm

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

More RTM instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2D, page 6-34 (XEND)
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  6. Intel: Intel Transactional Synchronization Extensions (Intel TSX) Memory and Performance Monitoring Update for Intel Processors (support article 000059422)
  7. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.38, July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.