XGETBV

XGETBV is how a program learns which register state the operating system has agreed to save. It reads the extended control register that ECX selects into EDX:EAX, at any privilege level, once the kernel has set CR4.OSXSAVE; before that it raises #UD. ECX = 0 reads XCR0, the set of XSAVE state components that the kernel enabled with XSETBV and switches between tasks. ECX = 1 reads XCR0 ANDed with XINUSE, the components not in their initial state, on processors that report it (CPUID leaf 0DH, sub-leaf 1, EAX bit 2). Any other value raises #GP.

Checking for AVX#

A CPUID bit says the processor has AVX; only XCR0 says the kernel saves YMM registers, and without that bit AVX instructions raise #UD. So the check that Intel’s optimization manual gives (Section 5.1.9) is CPUID leaf 1 for OSXSAVE (ECX bit 27) and AVX, then XGETBV with ECX = 0 for bits 1 and 2 (SSE and AVX state) both set. AVX-512 needs bits 5 to 7 as well (opmask and the two halves of the upper ZMM state), 0E6H with the others, and AMX bits 17 and 18, which Linux enables per process only on request. GCC 14 and Clang 23 at -O2 compile (_xgetbv(0) & 6) == 6 to xor ecx, ecx, XGETBV, NOT and TEST; the intrinsic needs -mxsave or an -march that has XSAVE, such as x86-64-v3 or sandybridge.

On Zen 5#

The probe’s Linux 7.1 guest set XCR0 to 2E7H: x87, SSE, AVX, the three AVX-512 components and PKRU (bit 9). Zen 5 ignored bits 63:32 of RCX, reading XCR0 for 1673D8DA00000000H, cleared bits 63:32 of RAX and RDX, and raised #GP for ECX = 2. With ECX = 1 it returned 2E7H as well: every enabled component was out of its initial state. Intel’s manual says the high half of RCX is ignored; AMD’s does not mention it. AMD’s Zen 5 guide lists XGETBV as microcoded, so a program reads XCR0 once at start-up and keeps the answer, as it does CPUID’s.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

r = cpuid_leaf(0xD, 1)               # EAX bit 2: ECX may be 1
if ecx == 0:                         # bits 63:32 of RCX do not count
    v = xcr0
elif ecx == 1 and r[0] >> 2 & 1:
    v = xinuse & xcr0
else:
    fault(GP, 0)
eax = v                              # RAX and RDX: bits 63:32 cleared
edx = v >> 32

Operands

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More XSAVE instructions

• XRSTOR
• XSAVE
• XSETBV