x86-64.net

Instruction

XLAT

Replaces AL with the byte at RBX plus AL, a table lookup; XLATB is the spelling without operands.

Extensions
Mnemonics
XLAT, XLATB
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

XLAT looks a byte up in a table of up to 256 bytes: RBX holds the table’s address, AL the index, and the byte found replaces AL. The index is unsigned, so AL = FFh reads entry 255, never one before the table, and bits 63:8 of RAX are neither read nor changed. Its classic use is converting text between character sets, such as ASCII to EBCDIC, one byte at a time in a loop with LODS and STOS.

The operand that is not one

The assembler accepts XLAT with a memory operand, xlat byte ptr [rbx], and XLATB without one; both are the single byte D7. The operand only documents the segment and address size: the address is always rBX plus AL, whatever register or displacement the operand names. A segment prefix changes the segment, which in 64-bit mode matters only for FS and GS, whose bases can be non-zero. A 67 prefix makes the address EBX plus AL, cut to 32 bits; Zen 5 ignored bits 63:32 of RBX that way.

Why compilers avoid it

Neither GCC 14 nor Clang 23 emits XLAT, even at -Os, where the one-byte encoding would save space: a lookup t[c] becomes a zero-extending MOVZX of the index, or a 32-bit MOV that clears the upper bits, and a byte load addressed with base and index. That needs no fixed registers, keeps RAX free, and works for indexes wider than a byte. XLAT also only writes AL, so the next instruction that reads EAX or RAX depends on the old upper bits. The instruction table of AMD’s Zen 5 guide lists XLAT as microcoded.

Lookups in vector registers

For tables small enough to sit in registers, the byte shuffles do the work of XLAT on many bytes at once: PSHUFB looks up 16 bytes in a 16-entry table (the low four bits of each index), and AVX-512’s VPERMB and VPERMI2B reach 64 and 128 entries; a full 256-entry table takes two or more such lookups and a blend.

Forms

Every encoding of XLAT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
XLAT XLATD7Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
ModelXLAT
Sandy Bridge, Broadwell, Skylake, Skylake-SP, Ice Lake5 / 0.5p23
Haswell7 / 0.75
Alder Lake, Sapphire Rapids7 / 0.4p0 p1 p2 p3 p5 p6 p10 p11
Lunar Lake7 / 0.33p0 p1 p2 p3 p4 p5 p20 p21 p22
Bonnell6 / 3p01
Silvermont3 / 1MEC
Piledriver6 / 0.5EX0 EX1
Zen, Zen 2100 / 0.25
Zen 3, Zen 45 / 0.33AGU0 AGU1 AGU2 LSU Load
Jaguar3 / 1LAGU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = low(rbx + al, ASIZE)         # AL unsigned, 0 to 255; with 67h, EBX + AL
                                 # wrapped to 32 bits
al = load(a, 8)                  # at DS:a, or FS:a or GS:a with a prefix

Run on AMD Zen 5 (EPYC 9645): 12 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
XLAT
m8 at [rBX+AL]implicitread
rBXimplicitread
ALimplicitread, write

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2D, page 6-38 (XLAT/XLATB)
  5. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.39, October 2026)
  6. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.