Instruction
XOR
Computes the bitwise exclusive OR of two operands; APX adds three-operand forms and forms that leave the flags unchanged.
- Extensions
- Forms
- 60 (24 Legacy, 36 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
XOR m8, imm8
XOR_MEMb_IMMb_80r6 | 80 /6 ib | Base instruction set |
XOR r8, imm8
XOR_GPR8_IMMb_80r6 | 80 /6 ib | Base instruction set |
XOR m16/32/64, imm16/32
XOR_MEMv_IMMz | 81 /6 iw/id | Base instruction set |
XOR r16/32/64, imm16/32
XOR_GPRv_IMMz | 81 /6 iw/id | Base instruction set |
XOR m8, imm8 not in 64-bit mode
XOR_MEMb_IMMb_82r6 | 82 /6 ib | Base instruction set |
XOR r8, imm8 not in 64-bit mode
XOR_GPR8_IMMb_82r6 | 82 /6 ib | Base instruction set |
XOR m16/32/64, imm8
XOR_MEMv_IMMb | 83 /6 ib | Base instruction set |
XOR r16/32/64, imm8
XOR_GPRv_IMMb | 83 /6 ib | Base instruction set |
XOR m8, r8
XOR_MEMb_GPR8 | 30 /r | Base instruction set |
XOR r8, r8
XOR_GPR8_GPR8_30 | 30 /r | Base instruction set |
XOR m16/32/64, r16/32/64
XOR_MEMv_GPRv | 31 /r | Base instruction set |
XOR r16/32/64, r16/32/64
XOR_GPRv_GPRv_31 | 31 /r | Base instruction set |
XOR r8, r8
XOR_GPR8_GPR8_32 | 32 /r | Base instruction set |
XOR r8, m8
XOR_GPR8_MEMb | 32 /r | Base instruction set |
XOR r16/32/64, r16/32/64
XOR_GPRv_GPRv_33 | 33 /r | Base instruction set |
XOR r16/32/64, m16/32/64
XOR_GPRv_MEMv | 33 /r | Base instruction set |
XOR AL, imm8
XOR_AL_IMMb | 34 ib | Base instruction set |
XOR rAX, imm16/32
XOR_OrAX_IMMz | 35 iw/id | Base instruction set |
LOCK XOR m8, imm8
XOR_LOCK_MEMb_IMMb_80r6 | 80 /6 ib | Base instruction set |
LOCK XOR m16/32/64, imm16/32
XOR_LOCK_MEMv_IMMz | 81 /6 iw/id | Base instruction set |
LOCK XOR m8, imm8 not in 64-bit mode
XOR_LOCK_MEMb_IMMb_82r6 | 82 /6 ib | Base instruction set |
LOCK XOR m16/32/64, imm8
XOR_LOCK_MEMv_IMMb | 83 /6 ib | Base instruction set |
LOCK XOR m8, r8
XOR_LOCK_MEMb_GPR8 | 30 /r | Base instruction set |
LOCK XOR m16/32/64, r16/32/64
XOR_LOCK_MEMv_GPRv | 31 /r | Base instruction set |
XOR r8, r8
XOR_GPR8i8_GPR8i8_APX | EVEX.LLZ.NP.MAP4.WIG 30 /rEVEX.LLZ.NP.MAP4.WIG 32 /r | APX_F |
XOR m8, r8
XOR_MEMi8_GPR8i8_APX | EVEX.LLZ.NP.MAP4.WIG 30 /r | APX_F |
XOR r8, r8 NF
XOR_GPR8i8_GPR8i8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG 30 /r NF=1EVEX.LLZ.NP.MAP4.WIG 32 /r NF=1 | APX_F + APX_NCI_NDD_NF |
XOR m8, r8 NF
XOR_MEMi8_GPR8i8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG 30 /r NF=1 | APX_F + APX_NCI_NDD_NF |
XOR r16/32/64, r16/32/64, imm8 NDD NF optional
XOR_GPRv_GPRv_IMM8_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 83 /6 ib ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
XOR r16/32/64, m16/32/64, imm8 NDD NF optional
XOR_GPRv_MEMv_IMM8_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 83 /6 ib ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
XOR r8, r8, r8 NDD NF optional
XOR_GPR8i8_GPR8i8_GPR8i8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG 30 /r ND=1 NF=0/1EVEX.LLZ.NP.MAP4.WIG 32 /r ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
XOR r8, m8, r8 NDD NF optional
XOR_GPR8i8_MEMi8_GPR8i8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG 30 /r ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
XOR r16/32/64, r16/32/64
XOR_GPRv_GPRv_APX | EVEX.LLZ.NP.MAP4.SCALABLE 31 /rEVEX.LLZ.NP.MAP4.SCALABLE 33 /r | APX_F |
XOR m16/32/64, r16/32/64
XOR_MEMv_GPRv_APX | EVEX.LLZ.NP.MAP4.SCALABLE 31 /r | APX_F |
XOR r16/32/64, r16/32/64 NF
XOR_GPRv_GPRv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 31 /r NF=1EVEX.LLZ.NP.MAP4.SCALABLE 33 /r NF=1 | APX_F + APX_NCI_NDD_NF |
XOR m16/32/64, r16/32/64 NF
XOR_MEMv_GPRv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 31 /r NF=1 | APX_F + APX_NCI_NDD_NF |
XOR r16/32/64, r16/32/64, r16/32/64 NDD NF optional
XOR_GPRv_GPRv_GPRv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 31 /r ND=1 NF=0/1EVEX.LLZ.NP.MAP4.SCALABLE 33 /r ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
XOR r16/32/64, m16/32/64, r16/32/64 NDD NF optional
XOR_GPRv_MEMv_GPRv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 31 /r ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
XOR r8, m8
XOR_GPR8i8_MEMi8_APX | EVEX.LLZ.NP.MAP4.WIG 32 /r | APX_F |
XOR r8, m8 NF
XOR_GPR8i8_MEMi8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG 32 /r NF=1 | APX_F + APX_NCI_NDD_NF |
XOR r8, r8, m8 NDD NF optional
XOR_GPR8i8_GPR8i8_MEMi8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG 32 /r ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
XOR r16/32/64, m16/32/64
XOR_GPRv_MEMv_APX | EVEX.LLZ.NP.MAP4.SCALABLE 33 /r | APX_F |
XOR r16/32/64, m16/32/64 NF
XOR_GPRv_MEMv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 33 /r NF=1 | APX_F + APX_NCI_NDD_NF |
XOR r8, r8, imm8 NDD NF optional
XOR_GPR8i8_GPR8i8_IMM8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG 80 /6 ib ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
XOR r8, m8, imm8 NDD NF optional
XOR_GPR8i8_MEMi8_IMM8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG 80 /6 ib ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
XOR r16/32/64, r16/32/64, m16/32/64 NDD NF optional
XOR_GPRv_GPRv_MEMv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 33 /r ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
XOR r8, imm8
XOR_GPR8i8_IMM8_APX | EVEX.LLZ.NP.MAP4.WIG 80 /6 ib | APX_F |
XOR m8, imm8
XOR_MEMi8_IMM8_APX | EVEX.LLZ.NP.MAP4.WIG 80 /6 ib | APX_F |
XOR r8, imm8 NF
XOR_GPR8i8_IMM8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG 80 /6 ib NF=1 | APX_F + APX_NCI_NDD_NF |
XOR m8, imm8 NF
XOR_MEMi8_IMM8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG 80 /6 ib NF=1 | APX_F + APX_NCI_NDD_NF |
XOR r16/32/64, imm16/32
XOR_GPRv_IMMz_APX | EVEX.LLZ.NP.MAP4.SCALABLE 81 /6 iw/id | APX_F |
XOR m16/32/64, imm16/32
XOR_MEMv_IMMz_APX | EVEX.LLZ.NP.MAP4.SCALABLE 81 /6 iw/id | APX_F |
XOR r16/32/64, imm16/32 NF
XOR_GPRv_IMMz_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 81 /6 iw/id NF=1 | APX_F + APX_NCI_NDD_NF |
XOR m16/32/64, imm16/32 NF
XOR_MEMv_IMMz_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 81 /6 iw/id NF=1 | APX_F + APX_NCI_NDD_NF |
XOR r16/32/64, r16/32/64, imm16/32 NDD NF optional
XOR_GPRv_GPRv_IMMz_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 81 /6 iw/id ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
XOR r16/32/64, m16/32/64, imm16/32 NDD NF optional
XOR_GPRv_MEMv_IMMz_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 81 /6 iw/id ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
XOR r16/32/64, imm8
XOR_GPRv_IMM8_APX | EVEX.LLZ.NP.MAP4.SCALABLE 83 /6 ib | APX_F |
XOR m16/32/64, imm8
XOR_MEMv_IMM8_APX | EVEX.LLZ.NP.MAP4.SCALABLE 83 /6 ib | APX_F |
XOR r16/32/64, imm8 NF
XOR_GPRv_IMM8_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 83 /6 ib NF=1 | APX_F + APX_NCI_NDD_NF |
XOR m16/32/64, imm8 NF
XOR_MEMv_IMM8_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 83 /6 ib NF=1 | APX_F + APX_NCI_NDD_NF |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to XOR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
__bextri_u32
unsigned int __bextri_u32(unsigned int a, const unsigned int b) |
|
__bextri_u64
unsigned long long __bextri_u64(unsigned long long a, const unsigned long long b) |
|
_get_ssp
unsigned long long _get_ssp(void) |
|
_kxor_mask32
__mmask32 _kxor_mask32(__mmask32 __A, __mmask32 __B) |
|
_kxor_mask64
__mmask64 _kxor_mask64(__mmask64 __A, __mmask64 __B) |
|
_kxor_mask8
__mmask8 _kxor_mask8(__mmask8 __A, __mmask8 __B) |
|
_mm512_kxor
__mmask16 _mm512_kxor(__mmask16 __A, __mmask16 __B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
I86 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
APX_F | APX_F | Nova Lake, Diamond Rapids |
APX_F_N3 | APX_F + APX_NCI_NDD_NF | Nova Lake, Diamond Rapids |
More General-purpose instructions
- NEG
- NOP
- NOT
- OR
- OUT
- OUTS
- PAUSE
- POP
- POPA
- POPF
- PUSH
- PUSHA
- PUSHF
- RCL
- RCR
- RET
- ROL
- ROR
- SALC
- SAR
- SBB
- SCAS
- SETcc
- SHL
- SHLD
- SHR
- SHRD
- STC
- STD
- STI
- STOS
- SUB
- TEST
- UD0
- UD1
- UD2
- UDB
- XADD
- XCHG
- XLAT
All 109 General-purpose instructions
More APX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
- Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.