XOR

XOR sets each bit of the result where its two operands differ. Beyond combining bit masks, compiled code uses it in three ways.

Zeroing a register#

xor eax, eax sets a register to 0. GCC 14 and Clang 23 at -O2 compile return 0; to it for int and long alike, since a 32-bit write clears bits 63:32 as well. It takes 2 bytes, where xor rax, rax takes 3 and mov eax, 0 takes 5.

Processors treat it as more than an XOR: the result cannot depend on the register’s old value, so they do not wait for it. Intel’s Optimization Reference Manual lists XOR and SUB of a register with itself among the dependency-breaking zero idioms, which from Sandy Bridge on need neither an issue port nor an execution unit (Section 3.5.1.7); AMD’s guide for Zen 5 lists both as zeroing idioms that execute in 0 cycles (Section 2.9.2).

The catch is the flags, which XOR writes: where they must survive, Intel’s manual recommends a MOV of 0 instead. The flags also decide where the XOR goes. For return a < b; both compilers emit xor eax, eax, cmp rdi, rsi and setl al: SETcc writes only AL, so the rest of EAX must be cleared beforehand, and an XOR placed after the CMP would destroy the flags that SETL reads.

Flipping bits#

XOR with a constant flips the bits set in the constant (x ^ 32 becomes xor eax, 32). For a bit whose number is in a register both compilers use BTC instead, so x ^ (1u << n) becomes btc eax, esi. Flipping every bit, x ^ -1, compiles to NOT, which is a byte shorter and leaves the flags alone.

Vector registers and memory#

The idiom carries over to vector registers: Intel’s list includes PXOR and XORPS of a register with itself and their VEX and EVEX forms, and AMD’s includes VPXOR and VXORPS. With LOCK and a memory destination, XOR flips bits atomically: atomic_fetch_xor compiles to lock xor qword ptr [rdi], rsi when its result is unused and to a CMPXCHG loop when it is used.

In the optimization guide

What the optimization guide says about XOR, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Zeroing and dependency-breaking idioms: xor eax, eax and sub eax, eax give zero whatever EAX held, and every core here recognizes them as it renames: the result needs no execution unit and does not wait for the old value, so the idiom also ends any chain through the register.
• Zeroing and dependency-breaking idioms: The idioms write the flags, as any xor or sub does.

Crestmont and Gracemont

• Integer execution: Moves, NOPs and zeroing idioms are handled at allocation and may never execute.

Ice Lake to Rocket Lake

• Integer execution: On Ice Lake, moves between general registers are no longer removed at renaming, and zeroing idioms take an execution unit. sources differ

Skylake to Cooper Lake

• Integer execution: xor, sub and the vector pxor, xorps, pandn, psub and pcmpgt of a register with itself zero it without an execution unit, four a cycle, for 32-bit and 64-bit and all vector registers.

Zen and Zen+

• Integer execution: Register-to-register moves of 32-bit and 64-bit general registers and of XMM registers, and xchg of general registers, take no execution cycle, while a YMM move renames only its lower half and moves the upper one in a pipe. sources differ

Zen 2

• Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole XMM and YMM registers take no execution cycle, where Zen 1 moves the upper half of a YMM register in a pipe. sources differ

Zen 3

• Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole XMM and YMM registers take no execution cycle, nor do the zeroing idioms such as xor eax, eax and vpxor, which also break the dependency on the old value; sbb eax, eax depends only on the carry flag, and pcmpeqd xmm0, xmm0 sets all ones without waiting. sources differ

Zen 4

• Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole vector registers take no execution cycle, nor do the zeroing idioms such as xor eax, eax and vpxor, which also break the dependency on the old value; sbb eax, eax depends only on the carry flag. sources differ

Zen 5

• Integer execution: Register-to-register moves of 32-bit and 64-bit general registers and of whole vector registers take no execution cycle, nor do the zeroing idioms such as xor eax, eax and vpxor, which also break the dependency on the old value.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

r = dest ^ sext(src)             # with LOCK: one atomic read-modify-write;
                                 # an immediate is sign-extended to OSIZE
if not nf:                       # NF=1 (APX) leaves the flags as they were
    of = cf = 0
    sf = msb(r)
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
dest.write(r)                    # a 32-bit register: bits 63:32 cleared;
                                 # XOR EAX, EAX zeroes all of RAX

r = src1 ^ sext(src2)            # an immediate is sign-extended to OSIZE
if not nf:                       # NF=1 leaves the flags as they were
    of = cf = 0
    sf = msb(r)
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
dest.write(r)                    # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

Attributes

What else XED records about the forms. How to read.

XOR m8, imm8 XOR m8, r8 XOR m16/32/64, imm16/32 XOR m16/32/64, imm8 XOR m16/32/64, r16/32/64

accepts a LOCK prefix

LOCK forms

locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SAR
• SBB
• SCAS
• SETcc
• SHL
• SHLD
• SHR
• SHRD
• STC
• STD
• STI
• STOS
• SUB
• TEST
• UD0
• UD1
• UD2
• UDB
• XADD
• XCHG
• XLAT

All 109 General-purpose instructions

More APX instructions

• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX
• SBB
• SETcc
• SHL
• SHLD
• SHLX
• SHR
• SHRD
• SHRX
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT
• URDMSR
• UWRMSR
• WRMSRNS
• WRSSD
• WRSSQ
• WRUSSD
• WRUSSQ

All 88 APX instructions