XORPD instruction (SSE2)

XORPD is the bitwise exclusive OR of two 128-bit values, the doubles' name for XORPS, whose page covers both of its uses: zeroing a register by XORing it with itself, and flipping signs with a constant of sign bits. VXORPD is the VEX and EVEX form, which zeroes a whole YMM or ZMM register from an xmm destination; this one writes over its first operand, leaves bits 128 and up as they were (see SSE and AVX) and needs a memory operand aligned to 16 bytes. Its encoding is XORPS’s with a 66 prefix, one byte longer.

Zen 5’s recorded cases show the bits at work: 0 XOR -0 gave -0, the denormal 15 times 2^-1074 XOR 1 gave 14 times 2^-1074, and -0 XOR an all-ones NaN gave 7FFFFFFFFFFFFFFFh, a NaN with its sign cleared. MXCSR stayed as it was.

Which compiler writes it

In our builds at -O2, with the default target and with -march=x86-64-v2, the two compilers part ways:

GCC 14 negates a double with xorpd xmm0, XMMWORD PTR .LC1[rip], the constant -0.0 in its low half, and a loop over doubles with XORPD against the same constant held in a register. It zeroes registers with PXOR, doubles included.
Clang 23 uses XORPS for negation and for _mm_xor_pd alike, and to zero _mm_setzero_pd(); it writes XORPD only to zero a register that double-precision instructions then use, as for the zero of a ReLU before MAXPD.

Intel’s optimization guide lists XORPD of a register with itself among the zero idioms that do not depend on the register’s old value (Section 3.5.1.7).

In the optimization guide

What the optimization guide says about XORPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Out-of-order and in-order execution: Silvermont recognizes xor zeroing at 32 bits and for XMM registers, not at 64 bits; Goldmont at 64 bits too.

Forms

Every encoding of XORPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`XORPD xmm, m128` XORPD_XMMxuq_MEMxuq	`66 0F 57 /r`	SSE2
`XORPD xmm, xmm` XORPD_XMMxuq_XMMxuq	`66 0F 57 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Result quadword i comes from quadword i of xmm1 and xmm2. Result quadwords 1 to 0: a1^b1, a0^b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.q[i] = xmm1.q[i] ^ src2.q[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`XORPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Which compiler writes it#