XORPS instruction (SSE)

XORPS computes the bitwise exclusive OR of two 128-bit values. Despite its name it does not treat them as singles: it neither reads nor writes MXCSR and raises no floating-point exception. Compiled code uses it for two things.

Zeroing a register

XORPS of a register with itself gives zero, whatever the register held, and processors know it. Intel’s optimization guide lists it among the zero idioms, which do not wait for the old value and, in the Sandy Bridge microarchitecture, need no execution unit (Section 3.5.1.7); AMD’s guide for Zen 5 lists VXORPS of a register with itself as a zeroing idiom that takes no cycles (Section 2.9.2).

Clang 23 at -O2 zeroes float and double scalars this way, and _mm_setzero_si128 too, but the accumulators of a vectorized integer sum with PXOR, which GCC 14 uses for all of them. The vendors’ guides advise matching the instruction to the data: Intel’s, for its Core microarchitecture, XORPS for floating-point data and PXOR for integers, because mixing the two on one register can cost time (Section 3.5.1.10); AMD’s, one data type for all the operations on a value (Section 2.11.2).

With AVX, vxorps xmm0, xmm0, xmm0 clears the whole YMM or ZMM register, since a VEX instruction zeroes the bits above its result, and both compilers zero 256- and 512-bit vectors that way. The EVEX form of VXORPS needs AVX512DQ; VPXORD is the AVX512F one.

Flipping signs

An XOR with a constant whose only set bits are the sign bits negates each element, and that is how GCC 14 and Clang 23 compile -x for a float: XORPS with a 16-byte constant of 80000000H (GCC uses XORPD for a double, Clang XORPS again). Unlike a subtraction from zero, it turns +0 into -0, changes the sign of a NaN and raises no exception. ANDPS with 7FFFFFFFH clears the sign bits for fabsf, and copysignf takes two ANDPS and an ORPS. The constant is a memory operand of the legacy form, so it must be aligned to 16 bytes, as the compilers’ constant pools are.

In the optimization guide

What the optimization guide says about XORPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Zeroing and dependency-breaking idioms: The vector registers have idioms of their own: pxor, xorps, xorpd, pandn, andnps, the integer subtractions psub and the comparisons pcmpgt of a register with itself, with their VEX and EVEX forms, which Intel counts for 512-bit registers only unmasked. sources differ

Silvermont to Goldmont Plus

Out-of-order and in-order execution: Silvermont recognizes xor zeroing at 32 bits and for XMM registers, not at 64 bits; Goldmont at 64 bits too.

Skylake to Cooper Lake

Integer execution: xor, sub and the vector pxor, xorps, pandn, psub and pcmpgt of a register with itself zero it without an execution unit, four a cycle, for 32-bit and 64-bit and all vector registers.

Forms

Every encoding of XORPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`XORPS xmm, m128` XORPS_XMMxud_MEMxud	`NP 0F 57 /r`	SSE
`XORPS xmm, xmm` XORPS_XMMxud_XMMxud	`NP 0F 57 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: a3^b3, a2^b2, a1^b1, a0^b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = xmm1.d[i] ^ src2.d[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`XORPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to XORPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_setzero_pd` `__m128d _mm_setzero_pd(void)`	`XORPS xmm, xmm` Legacy -msse2
`_mm_setzero_ps` `__m128 _mm_setzero_ps(void)`	`XORPS xmm, xmm` Legacy -msse
`_mm_setzero_si128` `__m128i _mm_setzero_si128(void)`	`XORPS xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Zeroing a register#

Flipping signs#