x86-64.net

Instruction

XRESLDTRK

Ends a TSXLDTRK region of an RTM transaction, so that later loads join the transaction's read set again.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of XRESLDTRK that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
XRESLDTRK XRESLDTRKF2 0F 01 E9TSX_LDTRK

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
ModelXRESLDTRK
Sapphire Rapids100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 0)[3] >> 16 & 1:
    fault(UD)                    # CPUID: no TSXLDTRK
if rtm_active:
    if ldtrk_suspended:
        ldtrk_suspended = 0      # loads join the read set again
    else:
        tx_abort(UNDEFINED)      # no region to end
# outside a transaction a NOP

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no TSXLDTRK, and every one raised an exception.

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to XRESLDTRK, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_xresldtrk void _xresldtrk(void)

XRESLDTRK Legacy -mtsxldtrk

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
TSX_LDTRK

TSX_LDTRK
CPUID.(EAX=07H,ECX=0):EDX[16] TSX_LDTRK

Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More TSXLDTRK instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2D, page 6-48 (XRESLDTRK)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.