XSAVEOPT

XSAVEOPT saves the same state as XSAVE, the components selected by XCR0 AND EDX:EAX, to an XSAVE area aligned to 64 bytes, in the same standard format, and may skip work in two ways that XSAVE does not take:

• The init optimization. A component in its initial state need not be written at all: its XSTATE_BV bit is cleared instead, and XRSTOR will initialize it from that bit.
• The modified optimization. A component that has not changed since the last XRSTOR may be skipped too, since the area already holds it. Intel’s Volume 1 (Section 13.9) allows this only when that XRSTOR read the same linear address at the same CPL, in the same VMX mode and in the standard format; AMD’s manual leaves it to the implementation.

Either way, the bytes of a skipped component stay as they were, so the area is complete only if the state was last restored from it. That suits an operating system’s context switch, which restores a thread’s state with XRSTOR and later saves it back into the same buffer.

Not for applications#

Depending on the operating system, a program’s XSAVEOPT may apply the modified optimization after an XRSTOR that another program ran, so Intel’s Volume 1 recommends that applications not use XSAVEOPT; XSAVE, or XSAVEC for a compacted area, is the safe choice.

MXCSR, and what Zen 5 wrote#

MXCSR and MXCSR_MASK are not subject to either optimization: XSAVEOPT stores them whenever SSE or AVX is requested. Zen 5 did so with only AVX requested (EDX:EAX = 4), writing 1F80H and 2FFFFH at bytes 24 to 31 and leaving the x87 bytes before them alone. Saving the x87 and SSE state with no unmasked x87 exception pending, it stored the last opcode and the instruction and data pointers as zeros, as AMD’s manual describes for FXSAVE.

Using it#

CPUID leaf 0DH, sub-leaf 1, reports XSAVEOPT in EAX bit 0. GCC 14 and Clang 23 need -mxsaveopt for _xsaveopt(p, mask); at -O2 it loads the mask into EDX:EAX and emits XSAVEOPT, and _xsaveopt64 emits the XSAVEOPT64 form, whose x87 pointers are 64-bit as in XSAVE64. The encoding is 0F AE /6 with a memory operand; with a 66 prefix the same bytes are CLWB. AMD’s Zen 5 guide lists XSAVEOPT as microcoded.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = mem.address
if a % 64:
    fault(GP, 0)
rfbm = (edx << 32 | eax) & xcr0      # the components to save
s = rfbm & xinuse                    # those in use; the others are not
bv = load(a + 512, 64)               # saved, their XSTATE_BV bits
store(a + 512, 64, bv & ~rfbm | s)   # cleared
if s & 1:                            # x87 state
    t = 0
    for j in range(8):
        if ftw >> 2 * j & 3 != 3:    # Rj not empty
            t |= 1 << j
    k = fsw >> 7 & 1                 # ES: Zen 5 stores the pointers
    store(a, 16, fcw)                # as zeros without it
    store(a + 2, 16, fsw)
    store(a + 4, 16, t)
    store(a + 6, 16, fop * k)
    if OSIZE == 64:                  # REX.W: 64-bit offsets
        store(a + 8, 64, fip * k)
        store(a + 16, 64, fdp * k)
    else:
        store(a + 8, 32, fip * k)
        store(a + 12, 32, fcs * k)
        store(a + 16, 32, fdp * k)
        store(a + 20, 32, fds * k)
    for i in range(8):
        store(a + 32 + 16 * i, 128, st[i])
if rfbm & 6:                         # MXCSR and its mask, in use or not
    store(a + 24, 32, mxcsr)
    store(a + 28, 32, mxcsr_mask)
if s & 2:                            # SSE: XMM0 to XMM15
    for i in range(16):
        store(a + 160 + 16 * i, 128, xmm[i])
if s & 4:                            # AVX: bits 255:128
    b = a + xsave_offset(2, 0)
    for i in range(16):
        v = ymm[i].dq[1]
        store(b + 16 * i, 128, v)
if s & 0x20:                         # AVX-512: k0 to k7
    b = a + xsave_offset(5, 0)
    for i in range(8):
        store(b + 8 * i, 64, opmask[i])
if s & 0x40:                         # bits 511:256 of zmm0-15
    b = a + xsave_offset(6, 0)
    for i in range(16):
        v = zmm[i].qq[1]
        store(b + 32 * i, 256, v)
if s & 0x80:                         # zmm16 to zmm31
    b = a + xsave_offset(7, 0)
    for i in range(16):
        store(b + 64 * i, 512, zmm[16 + i])
if s & 0x200:                        # PKRU, in 4 of its 8 bytes (Zen 5's XSAVE)
    store(a + xsave_offset(9, 0), 32, pkru)
# MPX's and AMX's components (3, 4, 17, 18) likewise
# It may also leave out a component that has not changed since an
# XRSTOR from the same area, as the processor tracks it

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

aligned memory operand; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.