Instruction
XSETBV
Writes EDX:EAX to the extended control register that ECX selects, such as XCR0, which enables AVX and other XSAVE state; ring 0 only.
- Extensions
- Forms
- 1 (1 Legacy)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
XSETBV
XSETBV | NP 0F 01 D1 | XSAVE + OSXSAVE |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
if CPL > 0 or ecx != 0: # XCR0 is the only one it writes
fault(GP, 0)
v = edx << 32 | eax
r = cpuid_leaf(0xD, 0) # the user components there are
if v & ~(r[3] << 32 | r[0]):
fault(GP, 0)
if not v & 1 or v & 6 == 4: # x87 always; AVX only with SSE
fault(GP, 0)
if v & 0x18 not in (0, 0x18): # MPX's two together
fault(GP, 0)
if v & 0xE0 and v & 0xE6 != 0xE6: # AVX-512's three together, with
fault(GP, 0) # AVX and SSE
if v >> 17 & 1 != v >> 18 & 1: # AMX's two together
fault(GP, 0)
xcr0 = vNot run on a processor: XSETBV runs at CPL 0 only.
Operands
| Operand | Kind | Action |
|---|---|---|
XSETBV | ||
ECX | implicit | read |
EDX | implicit | read |
EAX | implicit | read |
XCR0 | implicit | write |
Flags
None: XED records no flag that the forms test or change.
Attributes
What else XED records about the forms. How to read.
- All forms
- privileged: CPL 0 only; may abort a TSX transaction
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
XSAVE | XSAVE + OSXSAVE | Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 |
More XSAVE instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2D, page 6-70 (XSETBV)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
- Linux kernel documentation: Using XSTATE features in user space applications
- Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.