Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of XSETBV that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
XSETBV XSETBVNP 0F 01 D1XSAVE + OSXSAVE

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0 or ecx != 0:              # XCR0 is the only one it writes
    fault(GP, 0)
v = edx << 32 | eax
r = cpuid_leaf(0xD, 0)               # the user components there are
if v & ~(r[3] << 32 | r[0]):
    fault(GP, 0)
if not v & 1 or v & 6 == 4:          # x87 always; AVX only with SSE
    fault(GP, 0)
if v & 0x18 not in (0, 0x18):        # MPX's two together
    fault(GP, 0)
if v & 0xE0 and v & 0xE6 != 0xE6:    # AVX-512's three together, with
    fault(GP, 0)                     # AVX and SSE
if v >> 17 & 1 != v >> 18 & 1:       # AMX's two together
    fault(GP, 0)
xcr0 = v

Not run on a processor: XSETBV runs at CPL 0 only.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
XSETBV
ECXimplicitread
EDXimplicitread
EAXimplicitread
XCR0implicitwrite

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms
privileged: CPL 0 only; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

More XSAVE instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2D, page 6-70 (XSETBV)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  5. Linux kernel documentation: Using XSTATE features in user space applications
  6. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.