XTEST

XTEST tells code whether it is running inside a transaction: it clears ZF inside one, whether XBEGIN started it (RTM) or an XACQUIRE-prefixed lock instruction (HLE, lock elision), and sets ZF outside. CF, OF, SF, PF and AF are cleared either way; no register or memory changes. It is three bytes, 0F 01 D6, with no operands.

Why code asks#

Some instructions end every transaction: CPUID and PAUSE on any processor, Intel’s manual says, and on some processors x87 and MMX code, SYSCALL, VZEROUPPER and many more. A function that may be called both inside and outside a transaction, a spin-wait with PAUSE or a call into the kernel, can check XTEST first and take another path, or abort deliberately with XABORT and a code saying why. With HLE, XTEST is the only sign: the elided lock looks taken to the code that holds it, so nothing else shows the difference.

With -mrtm, GCC 14 and Clang 23 at -O2 compile _xtest() to xor eax, eax, xtest and setne al: the intrinsic returns 1 inside a transaction and 0 outside, the opposite sense of ZF.

Which CPUID bit#

Intel’s manual lets XTEST run when the processor has either HLE, CPUID.(EAX=7,ECX=0):EBX[4], or RTM, EBX[11], and raises #UD only when both are clear. XED’s records, and with them this page’s CPUID requirement, ask for RTM alone; its Operation section follows Intel’s manual. So on a processor with HLE and no RTM, XTEST is valid even though XBEGIN is not. XBEGIN’s page says where Intel disables TSX.

AMD’s manual defines no XTEST and marks both bits reserved. On this site’s Zen 5, whose CPUID reports neither, #UD was the result of both recorded cases.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

r = cpuid_leaf(7, 0)[1]
if not r >> 4 & 1 and not r >> 11 & 1:
    fault(UD)                    # CPUID: neither HLE nor RTM
zf = 0 if rtm_active or hle_active else 1
cf = of = sf = pf = af = 0
# inside a transaction ZF is clear. XED's records ask CPUID for RTM
# alone; Intel's manual takes HLE as well

Operands

Flags

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More RTM instructions

• XABORT
• XBEGIN
• XEND