x86 instruction set extensions
The x86 instruction set, part by part, with the CPUID bits, instructions and processors of each extension.
These are the extensions that the instruction reference covers. It started with every extension enumerated in CPUID leaf 07H sub-leaf 1 or a later leaf, which is what Intel and AMD have added since about 2020, and now covers the whole instruction set that Intel XED decodes: the general-purpose and system instructions, which XED counts as base sets rather than extensions, small extensions with a CPUID bit of their own, such as CMOV, BMI1, XSAVE and CET, and the extensions of AMD and VIA. Each page lists the extension’s instructions, its CPUID bits, and the processors that have it according to XED’s chip model, followed by AMD’s processors after Zen 2 from the CPU data of this site.
General-purpose
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| General-purpose | The integer arithmetic, logic, shift, bit, data-movement, jump and call, string, stack and flag instructions that every x86-64 processor runs, from those of the 8086 to those that 64-bit mode added. | 109 | Every x86-64 processor |
| CMOV | Conditional moves: CMOVcc copies a register or memory operand into a register only if a condition on the flags holds, so that code can choose between two values without a branch. | 1 | Every x86-64 processor |
| LAHF-SAHF | LAHF and SAHF in 64-bit mode, which the first x86-64 processors lacked there, so a CPUID bit says whether they work; they always work in the other modes. | 2 | Every x86-64 processor |
| POPCNT | POPCNT counts the set bits of a 16-, 32- or 64-bit operand in one instruction. | 1 | Nehalem, Westmere, Sandy Bridge and 40 more |
| LZCNT | LZCNT counts the leading zero bits of an operand; unlike BSR it has a defined result for zero, the operand size, and it reports that case in CF. | 1 | Haswell, Broadwell, Skylake and 30 more |
| BMI1 | The first Bit Manipulation Instructions: ANDN, BEXTR, BLSI, BLSMSK, BLSR and TZCNT, which combine, extract, isolate and count bits in one VEX-encoded instruction each (TZCNT is a legacy encoding). | 6 | Haswell, Broadwell, Skylake and 24 more |
| BMI2 | The second Bit Manipulation Instructions: BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX and SHRX, among them shifts and a multiply that leave the flags alone and bit deposit and extract. | 8 | Haswell, Broadwell, Skylake and 27 more |
| ADX | ADCX and ADOX add with a carry through CF alone or OF alone, so that two independent carry chains can run interleaved, as in multiplying big numbers. | 2 | Broadwell, Skylake, Comet Lake and 26 more |
| MOVBE | MOVBE loads or stores a value with its bytes reversed, converting between little- and big-endian data as it moves. | 1 | Haswell, Broadwell, Skylake and 35 more |
| RDRAND | RDRAND returns random numbers from a generator in the processor that its hardware entropy source keeps reseeding. | 1 | Ivy Bridge, Haswell, Broadwell and 34 more |
| RDSEED | RDSEED returns random numbers straight from the processor's hardware entropy source, meant for seeding software generators. | 1 | Broadwell, Skylake, Comet Lake and 31 more |
| APX | Intel's Advanced Performance Extensions double the general-purpose registers to 32 and give integer instructions a separate destination, optional flag suppression, conditional compares and paired pushes and pops, in 64-bit mode. | 88 | Nova Lake, Diamond Rapids |
| TBM | Trailing Bit Manipulation (TBM) computes masks and fills around the lowest set or clear bit of a register in one instruction, and adds BEXTR with an immediate. | 10 | Piledriver, Excavator, Steamroller |
Vector (SSE, AVX and AVX10)
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| SSE | SSE, the Streaming SIMD Extensions of the Pentium III: eight 128-bit XMM registers (16 in 64-bit mode), four-wide single-precision arithmetic, MXCSR and prefetches. | 65 | Every x86-64 processor |
| SSE2 | SSE2 extends the XMM registers to double precision and to integer vectors of every width, and adds LFENCE, MFENCE and MOVNTI; x86-64 code does its float and double arithmetic with it. | 124 | Every x86-64 processor |
| SSE3 | SSE3 adds horizontal additions and subtractions, the ADDSUB instructions for complex arithmetic, duplicating moves, LDDQU and the truncating x87 store FISTTP. | 11 | Every x86-64 processor |
| SSSE3 | Supplemental SSE3 adds byte shuffles with PSHUFB, byte alignment with PALIGNR, horizontal integer additions, absolute values, sign changes and two fixed-point multiplies. | 16 | Core (Merom, Conroe), Penryn, Nehalem and 44 more |
| SSE4.1 | SSE4.1 adds blends, rounding, dot products, sign and zero extension, element insert and extract, 32-bit multiplies, PTEST and streaming loads. | 49 | Penryn, Nehalem, Westmere and 41 more |
| SSE4.2 | SSE4.2 adds the string and text compares PCMPESTRI to PCMPISTRM, a 64-bit signed compare and the CRC32 instruction; POPCNT, often counted with it, has a CPUID bit of its own. | 6 | Nehalem, Westmere, Sandy Bridge and 40 more |
| AVX | AVX widens the vector registers to 256 bits (YMM) and adds the VEX encoding, whose instructions take a separate destination and have no alignment requirement; it brings floating-point arithmetic to 256 bits. | 253 | Sandy Bridge, Ivy Bridge, Haswell and 31 more |
| AVX2 | AVX2 brings integer vector instructions to 256 bits and adds gathers, permutes across 128-bit lanes, shifts by a count per element, broadcasts and masked moves. | 138 | Haswell, Broadwell, Skylake and 27 more |
| F16C | F16C converts packed half-precision values to single precision and back, for data stored in the compact 16-bit format. | 2 | Ivy Bridge, Haswell, Broadwell and 30 more |
| FMA | Fused multiply-add of packed and scalar singles and doubles, rounded once, in three operand orders (132, 213 and 231) that choose which operand the result replaces. | 60 | Haswell, Broadwell, Skylake and 28 more |
| AVX10.1 | The first version of the converged AVX10 vector ISA: the AVX-512 instruction set of Sapphire Rapids, enumerated by one feature bit and a version number instead of a feature bit per subset. | 686 | Nova Lake, Granite Rapids, Diamond Rapids |
| AVX10.2 | AVX10 version 2 adds to AVX10.1 bfloat16 arithmetic, FP8 conversions, saturating float-to-integer conversions, IEEE 754-2019 minimum and maximum, more dot products and scalar compares that set the flags for every relation; it is the first version Intel plans for both client and server processors. | 96 | Nova Lake, Diamond Rapids |
| AVX10_V2_AUX | Conversions from single precision to FP8 and between FP8 and the 6- and 4-bit formats of the OCP microscaling specification, defined with ACE. | 21 | none yet |
| AVX512ER | AVX512ER, the exponential and reciprocal instructions of the Xeon Phi processors, approximates 2^x, 1/x and 1/sqrt(x) in ZMM registers to within 2^-23 or 2^-28. | 10 | Knights Landing, Knights Mill |
| AVX512PF | AVX512PF, the gather and scatter prefetches of the Xeon Phi processors, brings the elements that a vector of indices addresses into the first- or second-level cache ahead of a gather or scatter. | 16 | Knights Landing, Knights Mill |
| AVX512_4FMAPS | AVX512_4FMAPS performs four fused multiply-adds of single-precision values in a row in one instruction, with four consecutive ZMM registers and four values from memory. | 4 | Knights Mill |
| AVX512_4VNNIW | AVX512_4VNNIW adds four dot products of signed words to doublewords in one instruction, with four consecutive ZMM registers and memory. | 2 | Knights Mill |
| AVX512-VP2INTERSECT | AVX512-VP2INTERSECT finds the elements that two vectors of doublewords or quadwords have in common and writes the answer as a pair of masks. | 2 | Tiger Lake, Zen 5, Zen 6 |
| AVX-VNNI | VEX-encoded forms of the AVX512-VNNI byte and word dot products, for processors and code without AVX-512. | 4 | Alder Lake, Arrow Lake, Panther Lake and 9 more |
| AVX-VNNI-INT8 | VEX-encoded dot products of 8-bit integers in every combination of signed and unsigned inputs, accumulated into 32-bit integers. | 6 | Arrow Lake, Panther Lake, Nova Lake and 4 more |
| AVX-VNNI-INT16 | VEX-encoded dot products of 16-bit integers with unsigned or mixed signed and unsigned inputs, accumulated into 32-bit integers. | 6 | Arrow Lake, Panther Lake, Nova Lake and 2 more |
| AVX-IFMA | VEX-encoded multiply-add of 52-bit unsigned integers into 64-bit accumulators, a building block for big-number arithmetic. | 2 | Arrow Lake, Panther Lake, Nova Lake and 4 more |
| AVX-NE-CONVERT | VEX-encoded conversions of bfloat16 and half-precision values to single precision and of single precision to bfloat16, which neither consult MXCSR nor raise floating-point exceptions. | 7 | Arrow Lake, Panther Lake, Nova Lake and 4 more |
| SSE4a | SSE4a, AMD's own addition to SSE3, extracts and inserts bit fields in XMM registers and stores scalar values non-temporally. | 4 | K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Bobcat, Dhyana, Excavator, Jaguar, Puma, Steamroller, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 |
| XOP | XOP, the extended operations of AMD's Bulldozer family, adds integer multiply-accumulate, horizontal adds, shifts and rotates per element, compares with a predicate and byte permutes, in an encoding of its own. | 55 | Bulldozer, Piledriver, Excavator, Steamroller |
| FMA4 | FMA4, AMD's fused multiply-add of the Bulldozer family, takes four operands, a separate destination and three sources, where FMA overwrites one of its three. | 20 | Bulldozer, Piledriver, Excavator, Steamroller |
x87, MMX and 3DNow!
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| x87 | The x87 floating-point unit computes in 80-bit extended precision on a stack of eight registers; x86-64 code still uses it for long double. | 90 | Every x86-64 processor |
| MMX | MMX, the first SIMD extension of x86, works on packed bytes, words and doublewords in eight 64-bit registers that share the x87 registers. | 47 | Every x86-64 processor |
| 3DNow! | 3DNow!, AMD's floating-point extension for MMX registers, computes with two single-precision values packed into one register, with fast reciprocal approximations. | 25 | K10 (Family 10h) |
Matrix (AMX and ACE)
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| AMX-TILE | The base of Advanced Matrix Extensions: eight tile registers of up to 1 KiB each, their configuration, and tile loads and stores. | 7 | Sapphire Rapids, Emerald Rapids, Granite Rapids and 1 more |
| AMX-INT8 | Tile matrix multiplication of 8-bit integers, signed or unsigned, accumulated into 32-bit integers. | 4 | Sapphire Rapids, Emerald Rapids, Granite Rapids and 1 more |
| AMX-BF16 | Tile matrix multiplication of bfloat16 values accumulated into single precision. | 1 | Sapphire Rapids, Emerald Rapids, Granite Rapids and 1 more |
| AMX-FP16 | Tile matrix multiplication of IEEE half-precision values accumulated into single precision. | 1 | Granite Rapids, Diamond Rapids |
| AMX-COMPLEX | Tile multiplication of complex numbers stored as half-precision pairs, producing the real or the imaginary part in single precision. | 2 | Granite Rapids, Diamond Rapids |
| AMX-FP8 | Tile matrix multiplication of 8-bit floating-point values in the E5M2 and E4M3 formats, accumulated into single precision. | 4 | Diamond Rapids |
| AMX-MOVRS | Tile loads with a read-shared hint, for data that many cores read. | 2 | Diamond Rapids |
| AMX-AVX512 | Moves rows of a tile into ZMM registers, optionally converting them to single precision, bfloat16 or half precision on the way. | 6 | Diamond Rapids |
| ACE | The AI Compute Extensions of the x86 Ecosystem Advisory Group: outer products of data in AVX10 vector registers accumulated into AMX tile registers, with block scale registers for microscaling formats. | 25 | none yet |
Cryptography
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| Key Locker | Key Locker turns AES keys into handles that only the processor can unwrap, so that software encrypts and decrypts without keeping the keys in memory. | 11 | Tiger Lake, Alder Lake, Arrow Lake and 4 more |
| AES-NI | AES-NI performs whole rounds of AES encryption and decryption on a 128-bit block in one instruction each, and helps with key expansion. | 12 | Westmere, Sandy Bridge, Ivy Bridge and 39 more |
| PCLMULQDQ | PCLMULQDQ multiplies two 64-bit polynomials over GF(2), without carries, into a 128-bit product. | 1 | Westmere, Sandy Bridge, Ivy Bridge and 39 more |
| SHA | The SHA extensions compute rounds and message schedules of SHA-1 and SHA-256 on XMM registers. | 7 | Cannon Lake, Ice Lake (client), Tiger Lake and 23 more |
| GFNI | Galois field instructions: byte multiplication in GF(2^8) and affine transformations of bytes by an 8x8 bit matrix, in legacy and VEX forms. | 6 | Ice Lake (client), Tiger Lake, Alder Lake and 16 more |
| VAES | VAES extends the AES round instructions to 256-bit YMM registers, one block per 128-bit lane; with AVX-512 or AVX10 they reach 512 bits. | 4 | Ice Lake (client), Tiger Lake, Alder Lake and 14 more |
| VPCLMULQDQ | VPCLMULQDQ performs one carry-less multiplication per 128-bit lane of a YMM register, and of a ZMM register with AVX-512 or AVX10. | 1 | Ice Lake (client), Tiger Lake, Alder Lake and 14 more |
| SHA512 | VEX-encoded message schedule and round instructions for SHA-384 and SHA-512. | 3 | Arrow Lake, Panther Lake, Nova Lake and 2 more |
| SM3 | VEX-encoded message expansion and round instructions for the SM3 hash function. | 3 | Arrow Lake, Panther Lake, Nova Lake and 2 more |
| SM4 | Key expansion and encryption rounds of the SM4 block cipher, VEX-encoded and, on processors with AVX10, EVEX-encoded up to 512 bits. | 2 | Arrow Lake, Panther Lake, Nova Lake and 2 more |
| VIA PadLock | VIA's PadLock units encrypt with AES, hash with SHA-1 and SHA-256, generate random numbers and multiply for modular arithmetic, each instruction working through a whole buffer in memory. | 9 | none yet |
Memory, caches and atomics
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| CMPXCHG16B | CMPXCHG16B compares and exchanges 16 bytes of memory atomically, for lock-free structures that update a pointer and a counter together. | 1 | Every x86-64 processor |
| CLFLUSH | CLFLUSH writes a cache line back to memory and removes it from every cache in the system. | 1 | Every x86-64 processor |
| CLFLUSHOPT | CLFLUSHOPT evicts a cache line like CLFLUSH but with weaker ordering, so that the flushes of many lines can overlap. | 1 | Skylake, Comet Lake, Cannon Lake and 28 more |
| CLWB | CLWB writes a modified cache line back to memory without necessarily evicting it, which makes stores to persistent memory durable at less cost than a flush. | 1 | Tiger Lake, Alder Lake, Arrow Lake and 19 more |
| CLDEMOTE | CLDEMOTE hints that a cache line should move from the core's own caches to a shared level, so that another core can read it sooner. | 1 | Sapphire Rapids, Emerald Rapids, Granite Rapids and 5 more |
| MOVDIRI | MOVDIRI writes a doubleword or quadword to memory with a direct store that bypasses the caches, for writing to device registers. | 1 | Tiger Lake, Alder Lake, Arrow Lake and 11 more |
| MOVDIR64B | MOVDIR64B copies 64 bytes from memory to a 64-byte aligned address as one direct store, the way to hand a work descriptor to a device. | 1 | Tiger Lake, Alder Lake, Arrow Lake and 11 more |
| RTM | Restricted Transactional Memory: XBEGIN starts a transaction whose memory updates all become visible on XEND, or are all rolled back on a conflict or an abort. | 4 | Haswell, Broadwell, Skylake and 12 more |
| TSXLDTRK | Suspend load address tracking: within an RTM transaction, XSUSLDTRK and XRESLDTRK bracket loads that stay out of the read set, so they cannot cause conflicts. | 2 | Sapphire Rapids, Emerald Rapids, Granite Rapids and 1 more |
| CMPccXADD | Atomic compare and add: compares a value in memory with a register and, if the condition holds, adds another register to memory, returning the old value either way. | 1 | Arrow Lake, Panther Lake, Nova Lake and 3 more |
| RAO-INT | Remote atomic operations: atomic add, and, or and xor on memory that return nothing, so the processor may perform them away from the core. | 4 | none yet |
| MOVRS | Loads and a prefetch with a read-shared hint, for data that many cores read but rarely write. | 6 | Nova Lake, Diamond Rapids |
| PREFETCHI | Prefetches code rather than data, from a RIP-relative address, into the cache hierarchy. | 2 | Granite Rapids, Diamond Rapids, Clearwater Forest and 2 more |
| PREFETCHWT1 | PREFETCHWT1 prefetches a cache line into the second-level cache in the exclusive state, ready for the processor to write it. | 1 | Knights Landing, Knights Mill |
| PREFETCHW | PREFETCH and PREFETCHW, which came with 3DNow!, fetch a cache line ahead of a read or a write; every AMD64 processor has them, and Intel's processors have PREFETCHW. | 3 | Every x86-64 processor |
| CLZERO | CLZERO zeroes a whole cache line with one instruction. | 1 | Zen, Zen+, Zen 2 and 4 more |
| MCOMMIT | MCOMMIT waits until earlier stores to memory with delayed error reporting have completed and says in CF whether any of them failed. | 1 | Zen 2, Zen 3 |
System
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| RDTSCP | RDTSCP reads the time-stamp counter together with IA32_TSC_AUX, where operating systems keep the number of the processor, after earlier instructions have executed. | 1 | Nehalem, Westmere, Sandy Bridge and 40 more |
| RDPID | RDPID reads IA32_TSC_AUX, where operating systems keep the number of the processor, without the time stamp that RDTSCP also returns. | 1 | Ice Lake (client), Tiger Lake, Alder Lake and 19 more |
| System | The instructions that operating systems, hypervisors and firmware use to control the processor: descriptor tables, control and model-specific registers, caches and TLBs, and the time-stamp counter. | 26 | Every x86-64 processor |
| SYSCALL/SYSRET | SYSCALL and SYSRET, the fast system call and return of 64-bit mode, which change privilege level with an entry point and segments held in MSRs instead of a gate in the IDT. | 2 | Every x86-64 processor |
| SYSENTER/SYSEXIT | SYSENTER and SYSEXIT, a fast system call and return that take the kernel's entry point and stack from MSRs, which 32-bit code uses on Intel processors. | 2 | Every x86-64 processor |
| VMX | VMX, Intel's virtualization extension (VT-x), lets a hypervisor run guests directly on the processor, each virtual processor described by a control structure (VMCS) in memory. | 13 | Core (Merom, Conroe), Penryn, Nehalem and 34 more |
| TDX | Intel TDX runs confidential virtual machines, trust domains, under the Intel TDX module, which the hypervisor and the guests call with the SEAM instructions. | 4 | Emerald Rapids, Granite Rapids, Diamond Rapids |
| SMX | SMX, the Safer Mode Extensions behind Intel TXT, adds GETSEC, whose leaf functions launch a measured environment from code that the processor has authenticated. | 1 | Core (Merom, Conroe), Penryn, Nehalem and 32 more |
| SGX | Intel SGX protects code and data in enclaves, memory that even the operating system cannot read; ENCLS and ENCLU perform its leaf functions, such as ECREATE and EENTER. | 3 | Skylake, Comet Lake, Cannon Lake and 11 more |
| FXSR | FXSAVE and FXRSTOR save and restore the x87, MMX and SSE registers and MXCSR in one 512-byte area; the operating system sets CR4.OSFXSR to say it saves SSE state this way. | 2 | Every x86-64 processor |
| XSAVE | The XSAVE feature set saves and restores processor state in numbered components that bitmaps select, so one mechanism covers x87, SSE, AVX, AVX-512, AMX and the state that later extensions add. | 4 | Sandy Bridge, Ivy Bridge, Haswell and 36 more |
| XSAVEOPT | XSAVEOPT saves like XSAVE but may skip state components that have not changed since the last XRSTOR or are in their initial state, which saves time on context switches. | 1 | Sandy Bridge, Ivy Bridge, Haswell and 36 more |
| XSAVEC | XSAVEC saves processor state in the compacted format, which packs the selected components together and leaves out those in their initial state. | 1 | Skylake, Comet Lake, Cannon Lake and 28 more |
| XSAVES | XSAVES and XRSTORS save and restore supervisor state components, such as the Processor Trace and CET registers, together with user state, in the compacted format; ring 0 only. | 2 | Skylake, Comet Lake, Cannon Lake and 28 more |
| MONITOR/MWAIT | MONITOR arms address monitoring and MWAIT waits in an optimized state for a store to the monitored range or an interrupt; kernels use them to idle processors. | 2 | Every x86-64 processor |
| WAITPKG | UMONITOR, UMWAIT and TPAUSE let user code wait in a power-saving state for a store to an address or for a time-stamp deadline, instead of spinning. | 3 | Alder Lake, Arrow Lake, Panther Lake and 8 more |
| SERIALIZE | SERIALIZE waits until all earlier instructions have completed and their stores have drained, without the register side effects of CPUID or the control transfer of IRET. | 1 | Alder Lake, Arrow Lake, Panther Lake and 7 more |
| SMAP | Supervisor Mode Access Prevention stops the kernel from reading or writing user pages, unless it sets the AC flag with STAC for the access and clears it again with CLAC. | 2 | Broadwell, Skylake, Comet Lake and 29 more |
| PKU | Protection keys for user pages: each page carries one of 16 keys, and RDPKRU and WRPKRU read and write the per-thread register that disables access or writes for each key. | 2 | Comet Lake, Cannon Lake, Ice Lake (client) and 19 more |
| FSGSBASE | RDFSBASE, RDGSBASE, WRFSBASE and WRGSBASE read and write the FS and GS segment bases in 64-bit mode, once the operating system has enabled them in CR4. | 4 | Ivy Bridge, Haswell, Broadwell and 35 more |
| INVPCID | INVPCID invalidates TLB entries by process-context identifier (PCID): of one address, of one context, or of all contexts with or without global pages; ring 0 only. | 1 | Haswell, Broadwell, Skylake and 22 more |
| CET | Control-flow Enforcement Technology: shadow stacks, which hold a copy of every return address that ordinary stores cannot change, and indirect branch tracking, which allows indirect jumps only to ENDBR instructions. | 14 | Tiger Lake, Alder Lake, Arrow Lake and 12 more |
| UINTR | User interrupts: a thread can send an interrupt with SENDUIPI to a thread on another core, whose handler then runs in user mode without the kernel. | 5 | Arrow Lake, Panther Lake, Nova Lake and 6 more |
| MPX | Memory Protection Extensions added bound registers and instructions that check pointers against bounds; Intel has deprecated MPX, and its core processors since Ice Lake lack it. | 7 | Skylake, Comet Lake, Cannon Lake and 7 more |
| PCONFIG | PCONFIG configures platform features through leaf functions selected by EAX, such as programming the keys of multi-key total memory encryption; ring 0 only. | 1 | Tiger Lake, Alder Lake, Arrow Lake and 9 more |
| WBNOINVD | WBNOINVD writes every modified cache line back to memory, as WBINVD does, but leaves the lines valid in the caches. | 1 | Tiger Lake, Alder Lake, Arrow Lake and 14 more |
| PTWRITE | PTWRITE lets software put a value of its own into the Intel Processor Trace stream, for example to mark events in a trace. | 1 | Alder Lake, Arrow Lake, Panther Lake and 10 more |
| ENQCMD | ENQCMD and ENQCMDS send a 64-byte command to the shared work queue of a device as one atomic write, tagged with a process address space ID, and learn from ZF whether the device took it. | 2 | Sapphire Rapids, Emerald Rapids, Granite Rapids and 3 more |
| MSRLIST | Reads or writes a list of up to 64 model-specific registers with one instruction. | 2 | Panther Lake, Nova Lake, Diamond Rapids and 2 more |
| WRMSRNS | A model-specific register write that, unlike WRMSR, is not serializing. | 1 | Panther Lake, Nova Lake, Diamond Rapids and 2 more |
| MSR_IMM | Forms of RDMSR and WRMSRNS that take the register number as an immediate and the value in any general-purpose register. | 2 | Clearwater Forest |
| USER_MSR | Lets user-mode code read and write the model-specific registers that the operating system allows in a bitmap. | 2 | Clearwater Forest |
| FRED | Flexible Return and Event Delivery replaces the IDT-based delivery of interrupts, exceptions and system calls with one mechanism, and adds ERETS and ERETU to return from it. | 2 | Panther Lake, Nova Lake, Diamond Rapids and 1 more |
| LKGS | Loads the GS segment from a selector but writes the descriptor's base address to the IA32_KERNEL_GS_BASE MSR, so a FRED kernel can change a thread's GS without losing its own GS base. | 1 | Panther Lake, Nova Lake, Diamond Rapids and 1 more |
| HRESET | Lets the kernel reset selected history that the processor keeps for its hardware prediction features, as enumerated in CPUID leaf 20H. | 1 | Alder Lake, Arrow Lake, Panther Lake and 5 more |
| PBNDKB | Encrypts and authenticates data with a key tied to the platform, for configuring Total Storage Encryption through PCONFIG. | 1 | Panther Lake, Nova Lake |
| IBHF | Indirect Branch History Fence: in ring 0 with BHI_DIS_S set, keeps branch history from before the fence from steering the predicted targets of later indirect branches. | 1 | Arrow Lake, Panther Lake, Nova Lake |
| LWP | Lightweight Profiling (LWP) lets a program count and sample its own events into a ring buffer in memory, without entering the kernel. | 4 | Bulldozer, Piledriver |
| SVM | SVM, AMD's virtualization extension (AMD-V), runs a guest with VMRUN from a control block in memory, the VMCB, until an intercepted event returns control to the hypervisor. | 8 | K10 (Family 10h), Bulldozer, Piledriver and 7 more |
| SEV-SNP | SEV-SNP, Secure Nested Paging, keeps a reverse map (RMP) of which guest owns each page, so that the hypervisor cannot remap or read the memory of an encrypted guest. | 4 | Zen 3, Zen 4, Zen 5 and 1 more |
| MONITORX | MONITORX and MWAITX are AMD's MONITOR and MWAIT for every privilege level, with a timeout on the wait. | 2 | Zen 2, Zen 3, Zen 4 and 2 more |
| RDPRU | RDPRU lets programs read the MPERF and APERF counters, which measure the processor's effective frequency, without a system call. | 1 | Zen 2, Zen 3, Zen 4 and 2 more |
| INVLPGB | INVLPGB invalidates TLB entries on every processor of a system at once, without interrupts between processors, and TLBSYNC waits for them to finish. | 2 | Zen 3, Zen 4, Zen 5 and 1 more |