x86 instruction set extensions
The x86 instruction set, part by part, with the CPUID bits, instructions and processors of each extension.
These are the extensions that the instruction reference covers. It started with every extension enumerated in CPUID leaf 07H sub-leaf 1 or a later leaf, which is what Intel and AMD have added since about 2020, and grows toward the whole instruction set: the general-purpose instructions, which XED counts as a base set rather than an extension, are here, and so are small extensions with a CPUID bit of their own, such as CMOV, POPCNT and BMI1. Each page lists the extension’s instructions, its CPUID bits, and the processors that have it according to XED’s chip model.
General-purpose
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| General-purpose | The integer arithmetic, logic, shift, bit, data-movement, jump and call, string, stack and flag instructions that every x86-64 processor runs, from those of the 8086 to those that 64-bit mode added. | 109 | Every x86-64 processor |
| CMOV | Conditional moves: CMOVcc copies a register or memory operand into a register only if a condition on the flags holds, so that code can choose between two values without a branch. | 1 | Every x86-64 processor |
| LAHF-SAHF | LAHF and SAHF in 64-bit mode, which the first x86-64 processors lacked there, so a CPUID bit says whether they work; they always work in the other modes. | 2 | Every x86-64 processor |
| POPCNT | POPCNT counts the set bits of a 16-, 32- or 64-bit operand in one instruction. | 1 | Nehalem, Westmere, Sandy Bridge and 36 more |
| LZCNT | LZCNT counts the leading zero bits of an operand; unlike BSR it has a defined result for zero, the operand size, and it reports that case in CF. | 1 | Haswell, Broadwell, Skylake and 26 more |
| BMI1 | The first Bit Manipulation Instructions: ANDN, BEXTR, BLSI, BLSMSK, BLSR and TZCNT, which combine, extract, isolate and count bits in one VEX-encoded instruction each (TZCNT is a legacy encoding). | 6 | Haswell, Broadwell, Skylake and 20 more |
| BMI2 | The second Bit Manipulation Instructions: BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX and SHRX, among them shifts and a multiply that leave the flags alone and bit deposit and extract. | 8 | Haswell, Broadwell, Skylake and 23 more |
| ADX | ADCX and ADOX add with a carry through CF alone or OF alone, so that two independent carry chains can run interleaved, as in multiplying big numbers. | 2 | Broadwell, Skylake, Comet Lake and 22 more |
| MOVBE | MOVBE loads or stores a value with its bytes reversed, converting between little- and big-endian data as it moves. | 1 | Haswell, Broadwell, Skylake and 31 more |
| RDRAND | RDRAND returns random numbers from a generator in the processor that its hardware entropy source keeps reseeding. | 1 | Ivy Bridge, Haswell, Broadwell and 30 more |
| RDSEED | RDSEED returns random numbers straight from the processor's hardware entropy source, meant for seeding software generators. | 1 | Broadwell, Skylake, Comet Lake and 27 more |
| APX | Intel's Advanced Performance Extensions double the general-purpose registers to 32 and give integer instructions a separate destination, optional flag suppression, conditional compares and paired pushes and pops, in 64-bit mode. | 88 | Nova Lake, Diamond Rapids |
Vector (AVX and AVX10)
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| AVX10.1 | The first version of the converged AVX10 vector ISA: the AVX-512 instruction set of Sapphire Rapids, enumerated by one feature bit and a version number instead of a feature bit per subset. | 686 | Nova Lake, Granite Rapids, Diamond Rapids |
| AVX10.2 | AVX10 version 2 adds to AVX10.1 bfloat16 arithmetic, FP8 conversions, saturating float-to-integer conversions, IEEE 754-2019 minimum and maximum, more dot products and scalar compares that set the flags for every relation; it is the first version Intel plans for both client and server processors. | 96 | Nova Lake, Diamond Rapids |
| AVX10_V2_AUX | Conversions from single precision to FP8 and between FP8 and the 6- and 4-bit formats of the OCP microscaling specification, defined with ACE. | 21 | none yet |
| AVX-VNNI | VEX-encoded forms of the AVX512-VNNI byte and word dot products, for processors and code without AVX-512. | 4 | Alder Lake, Arrow Lake, Panther Lake and 7 more |
| AVX-VNNI-INT8 | VEX-encoded dot products of 8-bit integers in every combination of signed and unsigned inputs, accumulated into 32-bit integers. | 6 | Arrow Lake, Panther Lake, Nova Lake and 3 more |
| AVX-VNNI-INT16 | VEX-encoded dot products of 16-bit integers with unsigned or mixed signed and unsigned inputs, accumulated into 32-bit integers. | 6 | Arrow Lake, Panther Lake, Nova Lake and 2 more |
| AVX-IFMA | VEX-encoded multiply-add of 52-bit unsigned integers into 64-bit accumulators, a building block for big-number arithmetic. | 2 | Arrow Lake, Panther Lake, Nova Lake and 3 more |
| AVX-NE-CONVERT | VEX-encoded conversions of bfloat16 and half-precision values to single precision and of single precision to bfloat16, which neither consult MXCSR nor raise floating-point exceptions. | 7 | Arrow Lake, Panther Lake, Nova Lake and 3 more |
Matrix (AMX and ACE)
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| AMX-TILE | The base of Advanced Matrix Extensions: eight tile registers of up to 1 KiB each, their configuration, and tile loads and stores. | 7 | Sapphire Rapids, Emerald Rapids, Granite Rapids and 1 more |
| AMX-INT8 | Tile matrix multiplication of 8-bit integers, signed or unsigned, accumulated into 32-bit integers. | 4 | Sapphire Rapids, Emerald Rapids, Granite Rapids and 1 more |
| AMX-BF16 | Tile matrix multiplication of bfloat16 values accumulated into single precision. | 1 | Sapphire Rapids, Emerald Rapids, Granite Rapids and 1 more |
| AMX-FP16 | Tile matrix multiplication of IEEE half-precision values accumulated into single precision. | 1 | Granite Rapids, Diamond Rapids |
| AMX-COMPLEX | Tile multiplication of complex numbers stored as half-precision pairs, producing the real or the imaginary part in single precision. | 2 | Granite Rapids, Diamond Rapids |
| AMX-FP8 | Tile matrix multiplication of 8-bit floating-point values in the E5M2 and E4M3 formats, accumulated into single precision. | 4 | Diamond Rapids |
| AMX-MOVRS | Tile loads with a read-shared hint, for data that many cores read. | 2 | Diamond Rapids |
| AMX-AVX512 | Moves rows of a tile into ZMM registers, optionally converting them to single precision, bfloat16 or half precision on the way. | 6 | Diamond Rapids |
| ACE | The AI Compute Extensions of the x86 Ecosystem Advisory Group: outer products of data in AVX10 vector registers accumulated into AMX tile registers, with block scale registers for microscaling formats. | 25 | none yet |
Cryptography
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| SHA512 | VEX-encoded message schedule and round instructions for SHA-384 and SHA-512. | 3 | Arrow Lake, Panther Lake, Nova Lake and 2 more |
| SM3 | VEX-encoded message expansion and round instructions for the SM3 hash function. | 3 | Arrow Lake, Panther Lake, Nova Lake and 2 more |
| SM4 | Key expansion and encryption rounds of the SM4 block cipher, VEX-encoded and, on processors with AVX10, EVEX-encoded up to 512 bits. | 2 | Arrow Lake, Panther Lake, Nova Lake and 2 more |
Memory, caches and atomics
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| CMPXCHG16B | CMPXCHG16B compares and exchanges 16 bytes of memory atomically, for lock-free structures that update a pointer and a counter together. | 1 | Every x86-64 processor |
| CLFLUSH | CLFLUSH writes a cache line back to memory and removes it from every cache in the system. | 1 | Every x86-64 processor |
| CLFLUSHOPT | CLFLUSHOPT evicts a cache line like CLFLUSH but with weaker ordering, so that the flushes of many lines can overlap. | 1 | Skylake, Comet Lake, Cannon Lake and 24 more |
| CLWB | CLWB writes a modified cache line back to memory without necessarily evicting it, which makes stores to persistent memory durable at less cost than a flush. | 1 | Tiger Lake, Alder Lake, Arrow Lake and 15 more |
| CLDEMOTE | CLDEMOTE hints that a cache line should move from the core's own caches to a shared level, so that another core can read it sooner. | 1 | Sapphire Rapids, Emerald Rapids, Granite Rapids and 5 more |
| CMPccXADD | Atomic compare and add: compares a value in memory with a register and, if the condition holds, adds another register to memory, returning the old value either way. | 1 | Arrow Lake, Panther Lake, Nova Lake and 3 more |
| RAO-INT | Remote atomic operations: atomic add, and, or and xor on memory that return nothing, so the processor may perform them away from the core. | 4 | none yet |
| MOVRS | Loads and a prefetch with a read-shared hint, for data that many cores read but rarely write. | 6 | Nova Lake, Diamond Rapids |
| PREFETCHI | Prefetches code rather than data, from a RIP-relative address, into the cache hierarchy. | 2 | Granite Rapids, Diamond Rapids, Clearwater Forest |
System
| Extension | Summary | Mnemonics | Processors |
|---|---|---|---|
| RDTSCP | RDTSCP reads the time-stamp counter together with IA32_TSC_AUX, where operating systems keep the number of the processor, after earlier instructions have executed. | 1 | Nehalem, Westmere, Sandy Bridge and 36 more |
| RDPID | RDPID reads IA32_TSC_AUX, where operating systems keep the number of the processor, without the time stamp that RDTSCP also returns. | 1 | Ice Lake (client), Tiger Lake, Alder Lake and 15 more |
| MSRLIST | Reads or writes a list of up to 64 model-specific registers with one instruction. | 2 | Panther Lake, Nova Lake, Diamond Rapids and 2 more |
| WRMSRNS | A model-specific register write that, unlike WRMSR, is not serializing. | 1 | Panther Lake, Nova Lake, Diamond Rapids and 2 more |
| MSR_IMM | Forms of RDMSR and WRMSRNS that take the register number as an immediate and the value in any general-purpose register. | 2 | Clearwater Forest |
| USER_MSR | Lets user-mode code read and write the model-specific registers that the operating system allows in a bitmap. | 2 | Clearwater Forest |
| FRED | Flexible Return and Event Delivery replaces the IDT-based delivery of interrupts, exceptions and system calls with one mechanism, and adds ERETS and ERETU to return from it. | 2 | Panther Lake, Nova Lake, Diamond Rapids |
| LKGS | Loads the GS segment from a selector but writes the descriptor's base address to the IA32_KERNEL_GS_BASE MSR, so a FRED kernel can change a thread's GS without losing its own GS base. | 1 | Panther Lake, Nova Lake, Diamond Rapids |
| HRESET | Lets the kernel reset selected history that the processor keeps for its hardware prediction features, as enumerated in CPUID leaf 20H. | 1 | Alder Lake, Arrow Lake, Panther Lake and 5 more |
| PBNDKB | Encrypts and authenticates data with a key tied to the platform, for configuring Total Storage Encryption through PCONFIG. | 1 | Panther Lake, Nova Lake |
| IBHF | Indirect Branch History Fence: in ring 0 with BHI_DIS_S set, keeps branch history from before the fence from steering the predicted targets of later indirect branches. | 1 | Arrow Lake, Panther Lake, Nova Lake |