x87, MMX and 3DNow!
3DNow! instructions (AMD)
3DNow!, AMD's floating-point extension for MMX registers, computes with two single-precision values packed into one register, with fast reciprocal approximations.
An AMD extension: Intel processors never had it, and in XED's chip model no AMD processor after K10 has it either.
- CPUID
- See the ISA sets below.
- Instructions
- 25 mnemonics
- Processors
- K10 (Family 10h)
3DNow! computes with two single-precision values in an MMX register, so it shares the MMX registers and needs FEMMS or EMMS before x87 code runs again. Its encoding is unusual: every instruction but FEMMS is 0F 0F with a ModR/M byte, and a byte after the operands selects the operation, which the encoding column writes last. The reciprocal and reciprocal square root come as an approximation (PFRCP, PFRSQRT) and Newton-Raphson steps that refine it (PFRCPIT1, PFRCPIT2). AMD’s extensions to 3DNow!, such as PSWAPD, have a CPUID bit of their own (3DNowExt). PREFETCH and PREFETCHW, which came with 3DNow!, outlived it.
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| FEMMS | Marks every x87 register empty at the end of 3DNow! or MMX code, exactly as EMMS does; AMD keeps it for older software. | 1 |
| PAVGUSB | Computes the averages of packed unsigned bytes of two MMX operands, rounded up; 3DNow!. | 2 |
| PF2ID | Converts two packed singles of an MMX register or memory to signed doublewords, saturating out-of-range values; 3DNow!. | 2 |
| PF2IW | Converts two packed singles to signed words, saturated and sign-extended to doublewords; AMD's 3DNow! extensions. | 2 |
| PFACC | Adds the two singles of each MMX operand, the first operand's sum going to the low half of the result; 3DNow!. | 2 |
| PFADD | Adds the two packed singles of two MMX operands; 3DNow!. | 2 |
| PFCMPEQ | Compares the packed singles of two MMX operands for equality, into all-ones or all-zeros doublewords; 3DNow!. | 2 |
| PFCMPGE | Tests the packed singles of two MMX operands for greater than or equal, into all-ones or all-zeros doublewords; 3DNow!. | 2 |
| PFCMPGT | Tests the packed singles of two MMX operands for greater than, into all-ones or all-zeros doublewords; 3DNow!. | 2 |
| PFMAX | Returns the larger of each pair of packed singles of two MMX operands; 3DNow!. | 2 |
| PFMIN | Returns the smaller of each pair of packed singles of two MMX operands; 3DNow!. | 2 |
| PFMUL | Multiplies the two packed singles of two MMX operands; 3DNow!. | 2 |
| PFNACC | Subtracts the high single from the low one within each MMX operand, the first operand's result going low; 3DNow! extensions. | 2 |
| PFPNACC | Subtracts the high single from the low one of the first operand and adds the singles of the second; 3DNow! extensions. | 2 |
| PFRCP | Approximates the reciprocal of the low single of an MMX register or memory, into both halves of the destination; 3DNow!. | 2 |
| PFRCPIT1 | Performs the first Newton-Raphson step that refines a PFRCP reciprocal approximation; 3DNow!. | 2 |
| PFRCPIT2 | Performs the second and last Newton-Raphson step that refines a PFRCP or PFRSQRT approximation; 3DNow!. | 2 |
| PFRSQIT1 | Performs the first Newton-Raphson step that refines a PFRSQRT reciprocal square root approximation; 3DNow!. | 2 |
| PFRSQRT | Approximates the reciprocal square root of the low single of an MMX register or memory, into both halves; 3DNow!. | 2 |
| PFSUB | Subtracts the packed singles of the second MMX operand from those of the first; 3DNow!. | 2 |
| PFSUBR | Subtracts the packed singles of the first MMX operand from those of the second, into the first; 3DNow!. | 2 |
| PI2FD | Converts two packed signed doublewords of an MMX register or memory to singles; 3DNow!. | 2 |
| PI2FW | Converts the signed words in the low halves of two doublewords to packed singles; AMD's 3DNow! extensions. | 2 |
| PMULHRW | Multiplies packed signed words of two MMX operands and keeps the high 16 bits of each product, rounded; 3DNow!. | 2 |
| PSWAPD | Swaps the two doublewords of an MMX register or memory into another MMX register; AMD's 3DNow! extensions. | 2 |
CPUID and processors
XED splits 3DNow! into 2 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors |
|---|---|---|
3DNOW | 3DNow | K10 (Family 10h) |
3DNOW_EXT | 3DNowExt | K10 (Family 10h) |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - AMD64 Architecture Programmer's Manual, Volume 5: 64-Bit Media and x87 Floating-Point Instructions (26569, rev. 3.16, November 2021), Wayback Machine copy of AMD's PDF
- AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.36, March 2024), Wayback Machine copy of AMD's PDF
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.