Matrix (AMX and ACE)
ACE
The AI Compute Extensions of the x86 Ecosystem Advisory Group: outer products of data in AVX10 vector registers accumulated into AMX tile registers, with block scale registers for microscaling formats.
- CPUID
- ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11]CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 - Instructions
- 25 mnemonics
- Processors
- None announced: XED lists these instructions only under its placeholder for future processors.
ACE (AI Compute Extensions) is a matrix extension specified by the x86 Ecosystem Advisory Group, whose whitepaper names AMD and Intel engineers as its authors. It is meant as the common matrix extension of x86, from laptops to servers. Where AMX multiplies tiles by tiles, ACE multiplies vectors: its instructions take two ZMM registers and accumulate their outer product into a tile.
Outer products
TOP4BSSD shows the idea. Each ZMM source holds 16 dwords of four bytes. For every pair (i, j), the instruction adds the four-byte dot product of dword i of the first source and dword j of the second to element (i, j) of a 16 × 16 tile of 32-bit integers: 1024 multiplications from two vector registers, 16 times as many as VPDPBSSD performs with the same inputs. The whitepaper argues that this keeps ACE close to AVX10: an outer product reads two vectors and updates an accumulator, like a vector multiply-add, so it fits the processor’s existing instruction scheduling.
The family covers signed and unsigned bytes (TOP4BSUD and its siblings), bfloat16 pairs (TOP2BF16PS), and the FP8 and INT8 formats of the OCP microscaling (MX) specification, for example TOP4MXHF8PS.
Block scaling
MX formats store blocks of small values with one shared power-of-two scale. ACE keeps those scales in a new 1024-bit block scale register: 8 groups of 16 E8M0 scale bytes, loaded from ZMM registers or memory with BSRMOVF, BSRMOVH and BSRMOVL and reset to 1.0 by BSRINIT. The MX outer products apply the scales of the groups their immediate selects, one for each source.
Tiles
ACE is a second palette of the AMX framework. Palette 2 has fixed dimensions, eight tiles of 16 rows of 64 bytes, so its LDTILECFG block holds only the palette number. Under palette 2 there are no tile loads and stores: tiles are accumulators, filled by the outer products and read out a row at a time into ZMM registers with TILEMOVROW and the converting TCVTROW instructions of AMX-AVX512. TILEMOVCOL and the register-to-tile direction of TILEMOVROW are new with ACE. A processor may implement palette 1, palette 2 or both.
The block scale register is a new XSAVE component (SCALEDATA, XCR0 bit 20, 128 bytes) next to AMX’s TILECFG (bit 17) and TILEDATA (bit 18).
Detection
ACE is CPUID.(EAX=07H,ECX=1):ECX[11], with its version in CPUID.(EAX=1DH,ECX=2):EAX[7:0]. The specification’s full check for ACE v1 also requires AVX10.2 (or AVX10.1 with AVX10_V1_AUX), AVX10_V2_AUX, CR4.OSXSAVE, and XCR0 bits 5 to 7, 17, 18 and 20. XED’s chip model has ACE only in a placeholder for future processors.
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| BSRINIT | ACE instruction that sets every byte of the block scale register to 7FH, the E8M0 encoding of a scale factor of 1.0. | 1 |
| BSRMOVF | ACE instruction that loads all 1024 bits of the block scale register from two ZMM sources, the first giving the upper half. | 2 |
| BSRMOVH | ACE instruction that moves the upper 512 bits of the block scale register to or from a ZMM register or memory. | 4 |
| BSRMOVL | ACE instruction that moves the lower 512 bits of the block scale register to or from a ZMM register or memory. | 4 |
| LDTILECFG | Loads the AMX tile configuration (palette, rows and bytes per row of each tile) from a 64-byte memory block and zeroes the tile registers. | 1 |
| STTILECFG | Stores the current AMX tile configuration to a 64-byte memory block. | 1 |
| TCVTROWD2PS | Moves one row of a tile to a ZMM register, converting its 32-bit integers to single precision. | 2 |
| TCVTROWPS2BF16H | Moves one row of a tile to a ZMM register, converting single precision to bfloat16 in the high half of each dword and zeroing the low half. | 2 |
| TCVTROWPS2BF16L | Moves one row of a tile to a ZMM register, converting single precision to bfloat16 in the low half of each dword and zeroing the high half. | 2 |
| TCVTROWPS2PHH | Moves one row of a tile to a ZMM register, converting single precision to half precision in the high half of each dword and zeroing the low half. | 2 |
| TCVTROWPS2PHL | Moves one row of a tile to a ZMM register, converting single precision to half precision in the low half of each dword and zeroing the high half. | 2 |
| TILEMOVCOL | ACE instruction that writes a ZMM register into one column of a tile register, the column chosen by an immediate or a register. | 2 |
| TILEMOVROW | Moves one row of a tile register to a ZMM register, or with ACE also the other way, the row chosen by an immediate or a register. | 4 |
| TILERELEASE | Returns the AMX tile configuration and all tile data to their initial state: unconfigured and zero. | 1 |
| TILEZERO | Sets every byte of a tile register to zero. | 1 |
| TOP2BF16PS | ACE rank-2 outer product: adds the dot product of each bfloat16 pair of one ZMM source with each pair of the other to a single-precision tile. | 1 |
| TOP4BSSD | ACE outer product of two ZMM registers of signed bytes, four per dword, accumulated into a tile of 32-bit integers. | 1 |
| TOP4BSUD | ACE outer product of a ZMM register of signed bytes with one of unsigned bytes, four per dword, accumulated into a tile of 32-bit integers. | 1 |
| TOP4BUSD | ACE outer product of a ZMM register of unsigned bytes with one of signed bytes, four per dword, accumulated into a tile of 32-bit integers. | 1 |
| TOP4BUUD | ACE outer product of two ZMM registers of unsigned bytes, four per dword, accumulated into a tile of 32-bit integers. | 1 |
| TOP4MXBF8PS | ACE outer product of E5M2 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | 1 |
| TOP4MXBHF8PS | ACE outer product of E5M2 by E4M3 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | 1 |
| TOP4MXBSSPS | ACE outer product of two ZMM registers of MX INT8 values, scaled by the block scale register and accumulated into a single-precision tile. | 1 |
| TOP4MXHBF8PS | ACE outer product of E4M3 by E5M2 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | 1 |
| TOP4MXHF8PS | ACE outer product of E4M3 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | 1 |
CPUID and processors
XED splits ACE into 3 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors in XED |
|---|---|---|
ACE_1 | ACE v1 | None yet: XED lists these instructions only under its placeholder for future processors. |
AMX_AVX512 | ACE v1 or AMX_AVX512 | Diamond Rapids |
AMX_TILE_BASE | ACE v1 or AMX_TILE | Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)
- x86 Ecosystem Advisory Group: The AI Compute Extensions (ACE) for x86, whitepaper version 1.0 (April 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.