x86-64.net

Cryptography

AES-NI

AES-NI performs whole rounds of AES encryption and decryption on a 128-bit block in one instruction each, and helps with key expansion.

CPUID
AES
CPUID.01H:ECX[25]
Instructions
12 mnemonics
Processors
Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
Linux flag
aes

AES-NI implements the Advanced Encryption Standard in hardware. AESENC and AESDEC each perform a full round on a 128-bit block with a round key, and AESENCLAST and AESDECLAST the final round; AESKEYGENASSIST and AESIMC help compute the round keys. VEX and EVEX forms of the round instructions, up to 512 bits, are on the pages of VAESENC and its relatives.

Instructions

Mnemonics with at least one form in AES-NI. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
AESDECPerforms one round of AES decryption on the block in an XMM register with the round key of the source.2
AESDECLASTPerforms the last round of AES decryption, without InvMixColumns, on a block with the round key of the source.2
AESENCPerforms one round of AES encryption on the block in an XMM register with the round key of the source.2
AESENCLASTPerforms the last round of AES encryption, without MixColumns, on a block with the round key of the source.2
AESIMCApplies InvMixColumns to an AES round key, turning encryption round keys into those of the equivalent decryption.2
AESKEYGENASSISTComputes the substituted and rotated words, with a round constant from an immediate, that AES key expansion needs.2
VAESDECPerforms one round of AES decryption on each 128-bit lane with the round key of the matching lane.2
VAESDECLASTPerforms the last round of AES decryption on each 128-bit lane with the round key of the matching lane.2
VAESENCPerforms one round of AES encryption on each 128-bit lane with the round key of the matching lane.2
VAESENCLASTPerforms the last round of AES encryption on each 128-bit lane with the round key of the matching lane.2
VAESIMCApplies InvMixColumns to an AES round key in an XMM register, the VEX form of AESIMC.2
VAESKEYGENASSISTComputes the substituted and rotated words, with a round constant from an immediate, that AES key expansion needs; VEX form.2

CPUID and processors

XED splits AES-NI into 2 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AES-NI. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AES

AES
CPUID.01H:ECX[25] AES

Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Note: Intel's manuals list AES-NI for Silvermont, as XED does; GCC's -march=silvermont leaves it out, and Intel's product pages show some of its Celeron parts without it.

Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

AVXAES

AES + AVX
CPUID.01H:ECX[25] AES
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.