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Matrix (AMX and ACE)

AMX-AVX512

Moves rows of a tile into ZMM registers, optionally converting them to single precision, bfloat16 or half precision on the way.

CPUID
ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11]
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 or AMX_AVX512
CPUID.(EAX=1EH,ECX=1):EAX[7]
Instructions
6 mnemonics
Processors
Diamond Rapids

AMX-AVX512 connects tiles with vector registers without going through memory. TILEMOVROW copies one row of a tile, 64 bytes, into a ZMM register; the TCVTROW instructions do the same while converting the row, for example TCVTROWD2PS from 32-bit integers to single precision and TCVTROWPS2BF16H from single precision to bfloat16. A kernel can then post-process a result tile, adding a bias or applying an activation function, with ordinary vector code.

The instructions need both the AMX state and the AVX-512 or AVX10 state enabled. The ACE specification includes them as well, which is why they can also be enabled by the ACE feature bits. Intel lists Diamond Rapids as the first processor with AMX-AVX512.

Instructions

Mnemonics with at least one form in AMX-AVX512. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
TCVTROWD2PSMoves one row of a tile to a ZMM register, converting its 32-bit integers to single precision.2
TCVTROWPS2BF16HMoves one row of a tile to a ZMM register, converting single precision to bfloat16 in the high half of each dword and zeroing the low half.2
TCVTROWPS2BF16LMoves one row of a tile to a ZMM register, converting single precision to bfloat16 in the low half of each dword and zeroing the high half.2
TCVTROWPS2PHHMoves one row of a tile to a ZMM register, converting single precision to half precision in the high half of each dword and zeroing the low half.2
TCVTROWPS2PHLMoves one row of a tile to a ZMM register, converting single precision to half precision in the low half of each dword and zeroing the high half.2
TILEMOVROWMoves one row of a tile register to a ZMM register, or with ACE also the other way, the row chosen by an immediate or a register.2

CPUID and processors

XED splits AMX-AVX512 into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AMX-AVX512. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AMX_AVX512

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

or

AMX_AVX512
CPUID.(EAX=1EH,ECX=1):EAX[7] AMX_AVX512

Diamond Rapids

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
  4. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.