x86-64.net

Matrix (AMX and ACE)

AMX-BF16

Tile matrix multiplication of bfloat16 values accumulated into single precision.

CPUID
AMX_BF16 (leaf 1EH)
CPUID.(EAX=1EH,ECX=1):EAX[1] or AMX_TILE + AMX_BF16
CPUID.(EAX=07H,ECX=0):EDX[24]
CPUID.(EAX=07H,ECX=0):EDX[22]
Instructions
1 mnemonic
Processors
Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
Linux flag
amx_bf16

AMX-BF16 adds TDPBF16PS, the bfloat16 matrix multiplication. It works like the AMX-INT8 instructions with pairs of bfloat16 values in each dword instead of four bytes, and accumulates in single precision.

Instructions

Mnemonics with at least one form in AMX-BF16. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
TDPBF16PSMultiplies two tiles of bfloat16 pairs and accumulates each row-by-column dot product into a single-precision tile.1

CPUID and processors

XED splits AMX-BF16 into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AMX-BF16. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AMX_BF16

AMX_BF16 (leaf 1EH)
CPUID.(EAX=1EH,ECX=1):EAX[1] AMX_BF16 (leaf 1EH)

or

AMX_TILE + AMX_BF16
CPUID.(EAX=07H,ECX=0):EDX[24] AMX_TILE
CPUID.(EAX=07H,ECX=0):EDX[22] AMX_BF16

Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.