x86-64.net

Matrix (AMX and ACE)

AMX-COMPLEX

Tile multiplication of complex numbers stored as half-precision pairs, producing the real or the imaginary part in single precision.

CPUID
AMX_COMPLEX (leaf 1EH)
CPUID.(EAX=1EH,ECX=1):EAX[2] or AMX_COMPLEX
CPUID.(EAX=07H,ECX=1):EDX[8]
Instructions
2 mnemonics
Processors
Granite Rapids, Diamond Rapids

AMX-COMPLEX treats each dword of a tile as a complex number with a half-precision real part and imaginary part. TCMMRLFP16PS accumulates the real parts of the products of two such matrices and TCMMIMFP16PS the imaginary parts, both in single precision, so a complex matrix product takes two instructions. Intel’s extensions reference lists it for Granite Rapids D and Diamond Rapids; XED’s chip model does not tell Granite Rapids D apart and lists it for Granite Rapids.

Instructions

Mnemonics with at least one form in AMX-COMPLEX. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
TCMMIMFP16PSMultiplies two tiles of complex half-precision numbers and accumulates the imaginary parts of the products into a single-precision tile.1
TCMMRLFP16PSMultiplies two tiles of complex half-precision numbers and accumulates the real parts of the products into a single-precision tile.1

CPUID and processors

XED splits AMX-COMPLEX into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AMX-COMPLEX. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AMX_COMPLEX

AMX_COMPLEX (leaf 1EH)
CPUID.(EAX=1EH,ECX=1):EAX[2] AMX_COMPLEX (leaf 1EH)

or

AMX_COMPLEX
CPUID.(EAX=07H,ECX=1):EDX[8] AMX_COMPLEX

Granite Rapids, Diamond Rapids

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.