x86-64.net

Matrix (AMX and ACE)

AMX-FP16

Tile matrix multiplication of IEEE half-precision values accumulated into single precision.

CPUID
AMX_FP16 (leaf 1EH)
CPUID.(EAX=1EH,ECX=1):EAX[3] or AMX_TILE + AMX_FP16
CPUID.(EAX=07H,ECX=0):EDX[24]
CPUID.(EAX=07H,ECX=1):EAX[21]
Instructions
1 mnemonic
Processors
Granite Rapids, Diamond Rapids

AMX-FP16 adds TDPFP16PS, which multiplies tiles of IEEE half-precision pairs and accumulates in single precision, the FP16 counterpart of TDPBF16PS. Intel introduced it with Granite Rapids.

Instructions

Mnemonics with at least one form in AMX-FP16. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
TDPFP16PSMultiplies two tiles of half-precision pairs and accumulates each row-by-column dot product into a single-precision tile.1

CPUID and processors

XED splits AMX-FP16 into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AMX-FP16. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AMX_FP16

AMX_FP16 (leaf 1EH)
CPUID.(EAX=1EH,ECX=1):EAX[3] AMX_FP16 (leaf 1EH)

or

AMX_TILE + AMX_FP16
CPUID.(EAX=07H,ECX=0):EDX[24] AMX_TILE
CPUID.(EAX=07H,ECX=1):EAX[21] AMX_FP16

Granite Rapids, Diamond Rapids

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.