CPUID
AMX_FP8
CPUID.(EAX=1EH,ECX=1):EAX[4]
Instructions
4 mnemonics
Processors
Diamond Rapids

AMX-FP8 adds matrix multiplications of the two 8-bit floating-point formats of the OCP OFP8 specification, E5M2 (BF8 in the mnemonics) and E4M3 (HF8), with four values in each dword and single-precision accumulation. TDPBF8PS and TDPHF8PS take the same format in both tiles; TDPBHF8PS and TDPHBF8PS mix them. Intel lists Diamond Rapids as the first processor with it.

Instructions

Mnemonics with at least one form in AMX-FP8. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
TDPBF8PSMultiplies two tiles of E5M2 FP8 values and accumulates each row-by-column dot product into a single-precision tile.1
TDPBHF8PSMultiplies a tile of E5M2 FP8 values by a tile of E4M3 FP8 values and accumulates each row-by-column dot product into a single-precision tile.1
TDPHBF8PSMultiplies a tile of E4M3 FP8 values by a tile of E5M2 FP8 values and accumulates each row-by-column dot product into a single-precision tile.1
TDPHF8PSMultiplies two tiles of E4M3 FP8 values and accumulates each row-by-column dot product into a single-precision tile.1

CPUID and processors

XED splits AMX-FP8 into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AMX-FP8. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AMX_FP8

AMX_FP8
CPUID.(EAX=1EH,ECX=1):EAX[4] AMX_FP8

Diamond Rapids

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.