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Matrix (AMX and ACE)

AMX-INT8

Tile matrix multiplication of 8-bit integers, signed or unsigned, accumulated into 32-bit integers.

CPUID
AMX_INT8 (leaf 1EH)
CPUID.(EAX=1EH,ECX=1):EAX[0] or AMX_TILE + AMX_INT8
CPUID.(EAX=07H,ECX=0):EDX[24]
CPUID.(EAX=07H,ECX=0):EDX[25]
Instructions
4 mnemonics
Processors
Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
Linux flag
amx_int8

AMX-INT8 adds the byte matrix multiplications, one instruction for each combination of signed and unsigned inputs: TDPBSSD, TDPBSUD, TDPBUSD and TDPBUUD.

Each computes C += A × B on three tiles. Every dword of A holds four consecutive bytes of one row of the matrix, and every dword of B holds the four matching bytes of one column, so B is stored with groups of four rows interleaved. For each element of C the instruction adds up the products of all those byte pairs along the row of A and the column of B and accumulates them in a 32-bit integer. With full 16 × 64-byte tiles, one instruction performs 16 × 16 × 64 = 16384 multiplications.

Instructions

Mnemonics with at least one form in AMX-INT8. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
TDPBSSDMultiplies two tiles of signed bytes, four per dword, and accumulates each row-by-column dot product into a tile of 32-bit integers.1
TDPBSUDMultiplies a tile of signed bytes by a tile of unsigned bytes and accumulates each row-by-column dot product into a tile of 32-bit integers.1
TDPBUSDMultiplies a tile of unsigned bytes by a tile of signed bytes and accumulates each row-by-column dot product into a tile of 32-bit integers.1
TDPBUUDMultiplies two tiles of unsigned bytes, four per dword, and accumulates each row-by-column dot product into a tile of 32-bit integers.1

CPUID and processors

XED splits AMX-INT8 into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AMX-INT8. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AMX_INT8

AMX_INT8 (leaf 1EH)
CPUID.(EAX=1EH,ECX=1):EAX[0] AMX_INT8 (leaf 1EH)

or

AMX_TILE + AMX_INT8
CPUID.(EAX=07H,ECX=0):EDX[24] AMX_TILE
CPUID.(EAX=07H,ECX=0):EDX[25] AMX_INT8

Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.